Georg Lehmann e1eabab6fe aco/optimizer_postRA: assume all registers are untrackable in loop headers ... Register writes from the pre-header might not be correct for any but the first loop iteration because they can be clobbered inside the loop. Foz-DB Navi21: Totals from 18 (0.01% of 134913) affected shaders: CodeSize: 251384 -> 251508 (+0.05%) Instrs: 47644 -> 47664 (+0.04%) Latency: 801801 -> 801852 (+0.01%) InvThroughput: 177579 -> 177593 (+0.01%) Copies: 4752 -> 4771 (+0.40%) Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8376 Fixes: d3b0f78110 ("aco/optimizer_postRA: Initialize loop header with preheader information") Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21540>		2023-02-28 04:27:05 +00:00
..
addrlib	amd: split GFX1103 into GFX1103_R1 and GFX1103_R2	2023-02-03 00:18:01 +00:00
ci	ci: Update traces expectations for gutting glsl opt_algebraic.	2023-02-28 03:36:09 +00:00
common	nir,amd: add and use nir_intrinsic_load_esgs_vertex_stride_amd	2023-02-24 21:27:24 +00:00
compiler	aco/optimizer_postRA: assume all registers are untrackable in loop headers	2023-02-28 04:27:05 +00:00
drm-shim	r300: use drm_shim_override	2022-11-16 14:37:47 +00:00
llvm	ac/llvm,radeonsi: lower fbfetch in abi	2023-02-27 09:43:53 +08:00
registers	amd/registers: only define SPI and COMPUTE registers in the 0xB000 range	2023-02-24 21:27:24 +00:00
vulkan	radv: split linker script for android since it requires different symbols	2023-02-27 14:34:16 +00:00
.clang-format	radv: Add nir_foreach_variable_with_modes to .clang-format	2022-12-09 07:07:10 +00:00
meson.build	meson: build radeon drm-shim also for r300 and r600	2022-11-16 14:37:47 +00:00