Add a new sc7180-trogdor-wormdingler-rev1-boe device type and move the
a618-vk job to it.
We'll have 12 boards, so we can increase parallelism and run fraction=1.
Update job settings and add one new expected fail, and skip a few
redundant tests in force-gmem mode.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39920>
The new kernel comes with CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 enabled which
is needed for the new sc7180-trogdor-wormdingler-rev1-boe device.
It also includes three small msm fixes and adds host support for running
VMs on arm64 for upcoming CI jobs.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39920>
The logic is supposed to find the stage with the maximum constlen to
trim for each time we have to trim a stage. But by not resetting
max_constlen each time, we would "trim" the same stage repeatedly,
leaving us thinking the total is below the limit when it actually isn't.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40127>
The HW uses ViewportIndex to select which GRAS_BIN_FOVEAT offset to use.
For normal 3d draws, either the ViewportIndex equals the view/layer or
we make the offset the same for all viewports/layers, but we aren't
aware of this in the 3d path and we always use viewport 0.
Use the HW offset 0 when subtracting the HW offset. This is a bit of a
hack, but it should work. This fixes LOAD_OP_LOAD with FDM.
Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39976>
For Gfx125 workloads that use systolic mode, this might mean
an extra PIPELINE_SELECT when flipping between a compute shader
that use the mode and another that doesn't use the mode
(or vice-versa).
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40014>
On i686-pc-linux-gnu, `offset` is larger than a long.
Signed-off-by: Jan Alexander Steffens (heftig) <heftig@archlinux.org>
Reviewed-by: Arcady Goldmints-Orlov <arcady@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40106>
Even when FDM isn't enabled, we can still emit patchpoints and duplicate
the viewport per-view or per-layer because the pipeline may include
VK_PIPELINE_CREATE_RENDERING_FRAGMENT_DENSITY_MAP_ATTACHMENT_BIT_EXT.
Before 25202d3e47 ("tu: Remove fdm argument from tu6_emit_tile_select")
we just silently skipped applying those patchpoints, but now we actually
apply them which means we need to re-emit viewport and scissor for
subsequent render passes.
Fixes: 25202d3e47 ("tu: Remove fdm argument from tu6_emit_tile_select")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39965>
There were 2 issues in the commit being fixed :
1. loading from the wrong surface state
2. not being able to have the optimization passes cleanup the
nir_vector_extract()
We fix the first issue by reusing the nir_vector_extract() pattern in
the broken places.
We fix the second issue by reworking the internal vec4 format we use
for passing around descriptor information. In particular we put the
set in its own component so that it can be easily optimized and the
vector extraction constant folded.
Fixes: e94cb92cb0 ("anv: use internal surface state on Gfx12.5+ to access descriptor buffers")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40076>
This test has been reported failing by Mesa CI at 8f4de30d.
However it was seen passing and randomly failing in manual
testing, so mark it as a flake.
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Simon Perretta <simon.perretta@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40117>
These don't really fit in pan_texture anymore, so move them to a
separate pan_buffer-file.
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39294>
The function pan_emit_bview_surface_with_stride is only used by
pan_buffer_texture_emit, which cannot use ASTC compressed formats
(already disabled in the format list).
As well as dropping this functionality, also inline the static function
in its only caller.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39294>
Vivante hardware exhibits floating-point interpolation inconsistencies
at the diagonal seam when the blitter uses a two-triangle quad for scaled
NEAREST blits. Enable the single-triangle blitter mode to match the
proprietary driver's approach of using one oversized triangle
clipped by scissor.
Fixes dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_*
Fixes dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_*
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39973>
When the blitter draws a textured quad using two triangles, the
interpolation at the diagonal seam between triangles can produce
slightly different texture coordinates for the same pixel position.
For NEAREST filtering this causes inconsistent texel selection at the
seam boundary, failing dEQP-GLES3 nearest_consistency_* tests.
V3D already works around a similar issue by reordering triangle indices
(use_index_buffer), but Vivante GPUs requires a stronger fix: drawing a
single oversized triangle and relying on scissor to clip to the actual
destination rectangle. This matches the approach used by Vivante's
proprietary driver.
Add a new use_single_triangle flag to blitter_context that drivers can
opt-in.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39973>
Quantization maps cannot work with cu_qp_delta_enabled = 1, and VCN1 is
unlikely to ever support it.
See 1dda9d56cb ("radv/video: Disable rate control modes for H265 encode on VCN1")
for additional details.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40052>
Originally, I thought I could get away with not doing this because we
were sizing up the framebuffer boundary to include the superblocks.
However, that's not actually good enough because it's not just about
when we do a clear. It's actually required for AFBC writes to work
properly with small tiles.
Fixes: 6a56d35705 ("pan/fb: Fill out our own descriptors")
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39324>
