Commit graph

6136 commits

Author SHA1 Message Date
Connor Abbott
fe45fefe57 intel/blorp: Use sized types for nir_tex_instr::dest_type
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7989>
2021-01-25 11:21:42 +01:00
Connor Abbott
68969cbcb7 brw/vec4: Don't convert tex dest type to glsl_type
We were using nir_tex_instr::dest_type to a glsl_type, then passing it
to emit_texture(), only to just check the number of components. Just
pass the number of components directly. This lets us delete
brw_glsl_base_type_for_nir_type, which was asserting with
nir_texop_all_samples_equal because it didn't handle bool32.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7989>
2021-01-25 11:21:42 +01:00
Lionel Landwerlin
65f7b93435 intel: silence unused var warnings in release builds
v2: Use ASSERTED

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4162
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8681>
2021-01-25 09:04:32 +00:00
Jason Ekstrand
cca257d596 anv: Advertise shaderInt64 on Gen11+
On Gen11, they took away our hardware int64 support.  We have lowering
for all of it in NIR except for subgroup ops.  Now that all the subgroup
ops are implemented, we can enable the feature.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:38 +00:00
Jason Ekstrand
8c2543d037 intel/fs: Implement umin/umax shuffle
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:38 +00:00
Jason Ekstrand
a6500236e3 intel/fs: Refactor our shuffle emit code
This adds an emit_scan_step helper which gives us a place to do
something a bit more interesting than emitting a single op.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:38 +00:00
Jason Ekstrand
44571c6a68 intel/fs: Properly lower 64-bit MUL on 64-bit-incapable platforms
There are two problems this commit solves:  First, is that the 64x64 MUL
lowering generates a Q MOV which, because of how late it runs in the
compile pipeline, it never gets removed.  Second, it generates 32x32
MULs and we have to run it a second time to lower those.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:38 +00:00
Jason Ekstrand
c80db6611a intel/fs: Support 64-bit CLUSTER_BROADCAST on Gen11+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:38 +00:00
Jason Ekstrand
b90921ec0c intel/fs: Support 64-bit SHUFFLE on Gen11+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:38 +00:00
Jason Ekstrand
cdedc82329 intel/fs: Support 64-bit SEL_EXEC on Gen11+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:37 +00:00
Jason Ekstrand
58bcb5401d intel/fs: QUAD_SWIZZLE requires packed data
We could probably support some strides if we tried hard enough but the
whole point of this opcode is to accelerate things with crazy Align16 or
crazy regions.  It's ok if we have to emit an extra MOV to get a packed
source.

Fixes: 8b4a5e641b "intel/fs: Add support for subgroup quad operations"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:37 +00:00
Jason Ekstrand
69a3559efd intel/reg,fs: Handle immediates properly in subscript()
Just returning the original type isn't what we want in basically any
case.  Mask and shift the immediate as needed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:37 +00:00
Jason Ekstrand
e797daba53 intel/compiler: Move brw_reg_type_for_bit_size to brw_reg_type.h
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:37 +00:00
Jason Ekstrand
4c8cbe9b13 intel/compiler: Return 1 for immediates in regs_read
Previously, we were returning 2 whenever the source was a Q type.  As
far as I can tell, the only reason why this hasn't blown up before is
that it was only ever used for VGRFs until the SWSB pass landed which
uses it for everything.  This wasn't a problem because Q types generally
aren't a thing on TGL.  However, they are for a small handful of
instructions.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
2021-01-22 18:38:37 +00:00
Jason Ekstrand
0e1447eb1b anv: Early-exit from cmd_buffer_flush_state
If we don't have any dynamic state, pipeline, or descriptor changes,
we can do a very quick early-exit instead of checking for a bunch of
stuff bit-by-bit.

Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8594>
2021-01-22 17:21:11 +00:00
Jason Ekstrand
18fc1dfea3 anv: Only flush descriptors used by the pipeline
Previously, if we had a pipeline transition from something which used,
say, tessellation to something which didn't and we ended up with
tessellation descriptors dirty, we could end up re-emitting far more
than necessary.  With this commit, we mask off unused stages so we only
update when necessary.

Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8594>
2021-01-22 17:21:11 +00:00
Jason Ekstrand
72c7a68c2b anv: Take the set of stages to flush in flush_descriptor_sets
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8594>
2021-01-22 17:21:11 +00:00
Jason Ekstrand
16a81cabb5 anv: Exit early from cmd_buffer_apply_pipe_flushes
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8594>
2021-01-22 17:21:11 +00:00
Lionel Landwerlin
28207669d0 anv: Fix stencil layout in render passes
We incorrectly utilize the stencil layouts structures even if we
should stick to the depth_stencil ones if the layout includes stencil.

v2: Don't forget stencil only layout (Nanley)
    Simplify callers of new helper functions (Nanley)

v3: Store VK_IMAGE_LAYOUT_UNDEFINED when no stencil is available (Nanley)
    Use a switch statement (Nanley)

v4: Consider all layouts but depth only to be potential stencil layouts (Lionel)

v5: Refactor helper in vk_image_layout_depth_only() and discard
    VkAttachmentDescriptionStencilLayoutKHR in
    VkAttachmentDescription2KHR if format is not depth/stencil.

v5: s/LAYOUT_COLOR_ATTACHMENT_OPTIMAL/LAYOUT_DEPTH_ATTACHMENT_OPTIMAL/ (Nanley)

v6: Fix overly harsh assert()

Fixes: c1c346f166 ("anv: implement VK_KHR_separate_depth_stencil_layouts")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4084
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8475>
2021-01-20 20:36:34 +00:00
Caio Marcelo de Oliveira Filho
77aa86a521 intel/fs: Separate SLM size calculation from encoding
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8486>
2021-01-19 21:49:04 +00:00
Abhishek Kumar
276e3927b5 intel: change urb max shader geometry for CML GT1
Below deqp cts failure is seen on CML GT1 only , GT2 all test
passes, changing the max shader geometry to 256 (previous 640)
fixes all failure tests.Similar issue on BDW GT1
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3173

dEQP-GLES31.functional.geometry_shading.layered.
		render_with_default_layer_cubemap
		render_with_default_layer_3d
		render_with_default_layer_2d_array

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4102

Signed-off-by: Abhishek Kumar <abhishek4.kumar@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8550>
2021-01-19 13:37:35 +00:00
Jason Ekstrand
63a431b81c anv: Add a trivial implementation of VK_KHR_deferred_host_operation
This isn't actually capable of deferring anything; it just trivially
returns success.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7735>
2021-01-18 10:09:51 -06:00
Lionel Landwerlin
9a54aa131e intel/perf: move gt_frequency to results
We want to unify things a bit between GL & Vulkan. So store those
values in the results rather than just in the GL query code.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
b7032d6776 intel/perf: link queries back to the gen_perf_config object
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
e79f112e4f intel/perf: add definition for generic perf counters
Those are not part of the OA report but will be used in upcoming
counters.

v2: Rename counter defines (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
bd7df91372 intel/perf: restructure i915 perf version checks
Trying to make things more readable.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
d8154c4006 intel/mi_builder: fix self modifying batches
So far we only write a maximum of 4 dwords further into the batch and
it seems just going over the CS prefetch was enough.

Turns out writing more dwords can delay the writes and we start
prefetching stuff that hasn't landed in memory yet.

This fixes the issue by stalling the CS to ensure the writes have
landed before we go over the prefetch.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 796fccce63 ("intel/mi-builder: add framework for self modifying batches")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
359312ae01 intel/mi_builder: optimize 64bit immediate register loads & memory stores
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
dbeca67a1d anv: don't disable KHR_performance_query in debug mode
This is useful to verify that queries are built properly and avoiding
to deal with i915-perf (typically under simulation).

v2: Remove likely() (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:22 +02:00
Lionel Landwerlin
d4b4d69d4d anv: add transfer usage for color/depth/stencil attachments
We sometimes use anv_layout_to_aux_state() to compute the aux state of
an image during the resolve operations at the end of a render
(sub)pass.

If we're dealing with a multisampled image that is created without a
transfer usage, our internal code might trigger a resolve using the
transfer layout (see genX_cmd_buffer.c:cmd_buffer_end_subpass), for
which the image doesn't the usage bit. The current code tries to AND
the 2 usages which won't have any bit in common, thus skipping all
checks below.

v2: Add the transfer usages depending on attachment usage (Lionel)

v3: Limit to samples > 1 (Jason) && DEPTH_STENCIL_ATTACHMENT_BIT (Lionel)

v4: Add transfer usage at image creation (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 54b525caf0 ("anv: Rework anv_layout_to_aux_state")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4037
Reviewed-by: Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8307>
2021-01-14 09:51:31 +02:00
Jason Ekstrand
f4902bb189 intel/genxml,anv,iris: Drop the legacy compute path from gen125.xml
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:28 -08:00
Jason Ekstrand
8f85e68dea anv: Enable push constants on gen12-hp
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:28 -08:00
Jason Ekstrand
369eab9420 intel/fs: Emit code for Gen12-HP indirect compute data
Reworks:
 * Jordan: Apply to gen > 12
 * Jordan: Adjust comment about loading constants

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:28 -08:00
Jason Ekstrand
4077ca1cc8 anv: Add a general state pool
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:28 -08:00
Jordan Justen
a6f8d59142 anv: Use COMPUTE_WALKER for gen12-hp
Rework: Rafael Antognolli, Jason Ekstrand
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:28 -08:00
Jordan Justen
91fe96cfbe anv: Don't use MEDIA_INTERFACE_DESCRIPTOR_LOAD for gen12-hp
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jordan Justen
435b272241 anv: Emit CFE_STATE for gen12-hp
Rework:
 * make scratch TODO. (Jason)
 * emit_compute_cs_state => emit_compute_state. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jason Ekstrand
b4ffbf1521 intel/fs: Allow compute dispatch without a pushed subgroup ID on Gen12-HP
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jordan Justen
9294193098 intel/compiler: Disable push constants on gen12-hp
We currently don't use push constants with the COMPUTE_WALKER command.
Make all uniforms to be pull constants.

The local group id previously was a push constant, but is now
available in R0.2[7:0].

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jason Ekstrand
b7c1ad00fc intel/tools: Decode COMPUTE_WALKER
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jordan Justen
cdc9e22a3a intel/genxml/gen125: Add CFE_STATE and COMPUTE_WALKER
Reworks:
 * Jason: Captalize COMPUTE_WALKER::BTD mode
 * Jason: Make COMPUTE_WALKER::InlineData an array
 * Jason: Remove stale fields, uint=>bool, add missing enum values.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jordan Justen
231c27adaf intel/common: Build mi_builder_test for gen 12.5
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8424>
2021-01-11 13:05:49 -08:00
Daniel Schürmann
bd8e84eb8d nir: replace .lower_sub with .has_fsub and .has_isub
This allows a more fine-grained control about whether
a backend supports one of these instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6597>
2021-01-11 19:13:51 +00:00
Erico Nunes
faaba0d6af nir/lower_vec_to_movs: don't vectorize unsupports ops
If the instruction being coalesced would be vectorized but the target
doesn't support vectorizing that op, skip coalescing.
Reuse the callbacks from alu_to_scalar to describe which ops should not
be vectorized.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6506>
2021-01-11 13:13:30 +00:00
Jason Ekstrand
2d08711a2c anv: Bump maxGeometryInputComponents to 128 on Gen8+
See 8e627af59d and 1e3e72e305 for why this may not be a good
idea on Gen7.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8397>
2021-01-08 23:17:26 +00:00
Rhys Perry
f199b7188b nir/load_store_vectorize: add data as callback args
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4202>
2021-01-07 16:34:53 +00:00
Rhys Perry
00c8bec47b nir: add nir_load_store_vectorize_options
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4202>
2021-01-07 16:34:53 +00:00
Michel Dänzer
1de2fd0cf2 wsi/x11: Always link against xcb-xrandr
The next commit will make use of it even without
VK_USE_PLATFORM_XLIB_XRANDR_EXT.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>
2021-01-07 14:57:45 +01:00
Christian Gmeiner
23c963f11b anv: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
2021-01-06 14:34:41 +00:00
Christian Gmeiner
c5a9270109 intel/compiler: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
2021-01-06 14:34:41 +00:00