9 commits

Author	SHA1	Message	Date
Jason Ekstrand	fdc3c5dd05	genxml/gen6,7,75: s/BackFace/Backface ... This is more consistent with gen8+ Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: "12.0" <mesa-stable@lists.freedesktop.org>	2016-06-03 19:29:28 -07:00
Jason Ekstrand	7120c75ec3	genxml: Make PIPE_CONTROL::CommandStreamerStallEnable a boolean ... This has been declared as a uint since SNB but it's only one bit. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>	2016-05-27 15:18:07 -07:00
Jordan Justen	ff41738871	genxml/hsw: Add L3 cache control registers ... These were added to the i965 driver in 5912da45a6. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>	2016-05-17 13:04:03 -07:00
Jason Ekstrand	1275c7c744	genxml: Fix the name of a 3DSTATE_SF/SBE field on gen6-7.5	2016-04-09 17:02:21 -07:00
Jordan Justen	7a03fb9ccb	genxml: Add L3 Cache Control register definitions ... Based on intel_reg.h (5912da45a6) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>	2016-03-24 23:49:53 -07:00
Jason Ekstrand	8c819b8c2b	genxml/gen75: Add the clear color bits to RENDER_SURFACE_STATE	2016-03-10 10:41:52 -08:00
Jason Ekstrand	3f8df795c1	genxml: Break output detail of 3DSTATE_SBE on gen7 into a struct ... This makes it work like 3DSTATE_SBE_SWIZ on gen8+ which is much more convenient.	2016-02-29 16:47:42 -08:00
Jason Ekstrand	82d2db80bb	genxml: Add MOCS fields to RENDER_SURFACE_STATE ... This allows us to set MOCS as a single uint32_t on all platforms.	2016-02-27 10:26:13 -08:00
Jason Ekstrand	f6d9587688	vulkan: Move XML and generator into src/intel/genxml	2016-02-18 10:30:29 -08:00

Renamed from src/vulkan/gen75.xml (Browse further)