Commit graph

15202 commits

Author SHA1 Message Date
Samuel Iglesias Gonsálvez
0449c93638 anv: enable shaderFloat64 feature
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-09 10:44:07 +01:00
Samuel Iglesias Gonsálvez
465204695f anv: enable float64 feature on supported platforms
v2:
- Remove image_ms_array initialization (Jason)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-09 10:44:07 +01:00
Juan A. Suarez Romero
c2acf97fcc nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes
So far, input_reads was a bitmap tracking which vertex input locations
were being used.

In OpenGL, an attribute bigger than a vec4 (like a dvec3 or dvec4)
consumes just one location, any other small attribute. So we mark the
proper bit in inputs_read, and also the same bit in double_inputs_read
if the attribute is a dvec3/dvec4.

But in Vulkan, this is slightly different: a dvec3/dvec4 attribute
consumes two locations, not just one. And hence two bits would be marked
in inputs_read for the same vertex input attribute.

To avoid handling two different situations in NIR, we just choose the
latest one: in OpenGL, when creating NIR from GLSL/IR, any dvec3/dvec4
vertex input attribute is marked with two bits in the inputs_read bitmap
(and also in the double_inputs_read), and following attributes are
adjusted accordingly.

As example, if in our GLSL/IR shader we have three attributes:

layout(location = 0) vec3  attr0;
layout(location = 1) dvec4 attr1;
layout(location = 2) dvec3 attr2;

then in our NIR shader we put attr0 in location 0, attr1 in locations 1
and 2, and attr2 in location 3 and 4.

Checking carefully, basically we are using slots rather than locations
in NIR.

When emitting the vertices, we do a inverse map to know the
corresponding location for each slot.

v2 (Jason):
- use two slots from inputs_read for dvec3/dvec4 NIR from GLSL/IR.

v3 (Jason):
- Fix commit log error.
- Use ladder ifs and fix braces.
- elements_double is divisible by 2, don't need DIV_ROUND_UP().
- Use if ladder instead of a switch.
- Add comment about hardware restriction in 64bit vertex attributes.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-09 10:42:22 +01:00
Samuel Iglesias Gonsálvez
3551a2d3ad isl: fix VA64 support for double and dvecN vertex attributes
We use *64*_PASSTHRU formats to upload vertex attributes of 64 bits
to avoid conversions. From the BDW PRM, Volume 2d, page 586
(VERTEX_ELEMENT_STATE):

     "When SourceElementFormat is set to one of the *64*_PASSTHRU
     formats, 64-bit components are stored in the URB without any
     conversion. In this case, vertex elements must be written as 128
     or 256 bits, with VFCOMP_STORE_0 being used to pad the output
     as required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
     component into the URB, Component 1 must be specified as
     VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE)
     in order to output a 128-bit vertex element, or Components 1-3 must
     be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
     element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
     to be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
     element."

v2,v3 (Jason):
- Don't delete unused formats.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-09 09:10:13 +01:00
Juan A. Suarez Romero
1c9483f48e anv/pipeline: get map for double input attributes
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-09 09:10:13 +01:00
Samuel Iglesias Gonsálvez
cc4ff6c2a0 spirv: add support for doubles to OpSpecConstant
v2 (Jason):
- Fix indent in radv change
- Add vtn_u64_literal() helper to take 64 bits (Jason)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-09 09:10:13 +01:00
Jason Ekstrand
faa1edeeb7 anv/pipeline: Call NIR passes using NIR_PASS_V
This lets us get validation without having to do it manually.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2017-01-07 15:45:09 -08:00
Jason Ekstrand
43e0b0d4b2 anv/pipeline: Only call remove_dead_variables once
It can handle multiple modes at a time now so there's no reason to call
it repeatedly.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2017-01-07 15:45:09 -08:00
Jason Ekstrand
2d7bed6158 anv/formats: Use the real format for B4G4R4A4_UNORM_PACK16 on gen8
Because border color is handled pre-swizzle, when we move the alpha
channel around in the format, the OPAQUE_BLACK border colors don't work
correctly on B4G4R4A4_UNORM_PACK16 with the hack.  This fixes the
following Vulkan CTS tests on Broadwell:

dEQP-VK.pipeline.sampler.view_type.2d_array.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
dEQP-VK.pipeline.sampler.view_type.1d_array.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
dEQP-VK.pipeline.sampler.view_type.2d.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
dEQP-VK.pipeline.sampler.view_type.1d.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
dEQP-VK.pipeline.sampler.view_type.3d.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2017-01-06 16:44:15 -08:00
Jason Ekstrand
4e7958fb13 isl: Mark A4B4G4R4_UNORM as supported on gen8
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-dev@lists.freedesktop.org>
2017-01-06 16:44:15 -08:00
Lionel Landwerlin
a8eeb089c0 anv: fix multiple creation with internal failure
The specification section 9.4 says :

   When an application attempts to create many pipelines in a single
   command, it is possible that some subset may fail creation. In that
   case, the corresponding entries in the pPipelines output array will
   be filled with VK_NULL_HANDLE values. If any pipeline fails
   creation (for example, due to out of memory errors), the
   vkCreate*Pipelines commands will return an error code. The
   implementation will attempt to create all pipelines, and only
   return VK_NULL_HANDLE values for those that actually failed.

Fixes :

   dEQP-VK.api.object_management.alloc_callback_fail_multiple.graphics_pipeline
   dEQP-VK.api.object_management.alloc_callback_fail_multiple.compute_pipeline

v2: C is hard let's go shopping (Lionel)

v3: Remove unnecessary condition in for loops (Lionel)

v4: Document why we return on first failure (Eduardo)
    Move i declaration inside for() (Eduardo)

v5: Move array cleanup out of loop (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-01-05 21:09:09 +00:00
Lionel Landwerlin
36b5f1d200 spirv: compute push constant access offset & range
v2: Move relative push constant relative offset computation down to
    _vtn_load_store_tail() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-04 21:14:17 +00:00
Ilia Mirkin
1f13cb8b15 anv,radv: disable StorageImageWriteWithoutFormat for now
The SPIR-V capability isn't even marked as enabled, and there are no
tests in Vulkan-CTS. Per Jason Ekstrand, this won't work in anv as such
write-only surfaces require additional setup which is currently not
performed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-12-31 16:38:00 -05:00
Jason Ekstrand
134a5ad31c nir: Make nir_copy_deref follow the "clone" pattern
We rename it to nir_deref_clone, re-order the sources to match the other
clone functions, and expose nir_deref_var_clone.  This past part, in
particular, lets us get rid of quite a few lines since we no longer have
to call nir_copy_deref and wrap it in deref_as_var.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-12-30 12:38:04 -08:00
Ilia Mirkin
c633f228b4 anv: add support for extended texture gather
Now that the SPIR-V -> NIR translation is in place, no additional logic
is required.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-12-29 20:43:33 -05:00
Dave Airlie
de7dd4d621 spirv: add interface for drivers to define support extensions.
I expect over time the struct contents will change as all
drivers support stuff etc, but for now this should be a good
starting point.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-12-28 22:43:17 +00:00
Chad Versace
d6545f2345 anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0
The spec implicitly allows the incoming count to be 0. From the Vulkan
1.0.38 spec, Section 4.1 Physical Devices:

    If the value referenced by pQueueFamilyPropertyCount is not 0 [then
    do stuff].

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-27 12:31:34 -08:00
Damien Grassart
75252826e8 anv: return count of queue families written
The Vulkan spec indicates that
vkGetPhysicalDeviceQueueFamilyProperties() should overwrite
pQueueFamilyPropertyCount with the number of structures actually
written to pQueueFamilyProperties.

Signed-off-by: Damien Grassart <damien@grassart.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Cc: mesa-stable@lists.freedesktop.org
2016-12-27 10:15:47 -08:00
Jordan Justen
097c9dc2d4 intel/blorp_blit: Fix max blit size for gen6
Fixes ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_stencil_blit

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-12-26 08:50:21 -08:00
Timothy Arceri
eda3ec7957 i965: use nir_lower_indirect_derefs() for GLSL
This moves the nir_lower_indirect_derefs() call into
brw_preprocess_nir() so thats is called by both OpenGL and Vulkan
and removes that call to the old GLSL IR pass
lower_variable_index_to_cond_assign()

We want to do this pass in nir to be able to move loop unrolling
to nir.

There is a increase of 1-3 instructions in a small number of shaders,
and 2 Kerbal Space program shaders that increase by 32 instructions.
The changes seem to be caused be the difference in the GLSL IR vs
NIR variable index lowering passes. The GLSL IR pass creates a
simple if ladder for arrays of size 4 or less, while the NIR pass
implements a binary search for all arrays regardless of size.

Shader-db results BDW:

total instructions in shared programs: 13021176 -> 13021819 (0.00%)
instructions in affected programs: 57693 -> 58336 (1.11%)
helped: 20
HURT: 190

total cycles in shared programs: 299805580 -> 299750826 (-0.02%)
cycles in affected programs: 2290024 -> 2235270 (-2.39%)
helped: 337
HURT: 442

total fills in shared programs: 19984 -> 19984 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0

LOST:   4
GAINED: 0

V2: remove the do_copy_propagation() call from the i965 GLSL IR
linking code. This call was added in f7741c5211 but since we are
moving the variable index lowering to NIR we no longer need it and
can just rely on the nir copy propagation pass.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Francisco Jerez
79d08ed3d2 anv: Fix uniform and storage buffer offset alignment limits.
This fixes a regression in a bunch of image store vulkan CTS tests
from commit ad38ba1134, which started
using OWORD block read messages to implement UBO loads.  The reason
for the failure is that we were giving bogus buffer alignment limits
to the application (1B), so the CTS would happily come back with
descriptor sets pointing at not even word-aligned uniform buffer
addresses.

Surprisingly the sampler messages used to fetch pull constants before
that commit were able to cope with the non-texel aligned addresses,
but the dataport messages used to fetch pull constants after that
commit and the ones used to access storage buffers (before and after
the same commit) aren't as permissive with unaligned addresses.

Cc: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99097
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-16 14:12:54 -08:00
Kenneth Graunke
e0c1ec3b09 genxml: Make Gen8 3DSTATE_DS SIMD8 enable work like Gen9+.
This will let us avoid ifdefs.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-12-14 14:59:06 -08:00
Kenneth Graunke
000b563a1b genxml: Rename "DS Function Enable" to "Function Enable".
This makes Gen7/7.5 match Gen8-9.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-12-14 14:59:06 -08:00
Chad Versace
72ffe8318d anv: Reject VkMemoryAllocateInfo::allocationSize == 0
The Vulkan 1.0.33 spec says "allocationSize must be greater than 0".

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-12-14 12:04:58 -08:00
Grazvydas Ignotas
b58d1eecc6 intel/aubinator: fix 32bit shift overflow warning
Doesn't look like this can work on 32bit, just rids of annoying
warning.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2016-12-11 20:04:15 +01:00
Grazvydas Ignotas
3a1b15c392 anv: fix release build unused variable warnings
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2016-12-11 20:03:14 +01:00
Edward O'Callaghan
efe9d1cde3 anv: Clean up some unused variables
Following on from the spirit of commit 011e5570f.

Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-10 11:59:59 +11:00
Jordan Justen
d6526d7247 intel/blorp_blit: Add split_blorp_blit_debug switch
Enabling this debug switch causes surface shrinking to happen by
default, and lowers the surface size limit which causes blorp blits to
be split.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
da381ae647 intel/blorp_blit: Enable splitting large blorp blits
Detect when the surface sizes are too large for a blorp blit. When it
is too large, the blorp blit will be split into a smaller operation
and attempted again.

For gen7, this fixes the cts test:

ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit

It will also enable us to increase our renderable size from 8k x 8k to
16k x 16k.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
efea8e7244 intel/blorp_blit: Move RGB=>R conversion to follow blit splitting
In blorp_copy, when RGB surfaces are copied, we convert the
destination surface to a Red only surface, but 3 times as wide. This
introduces an implicit restriction of "mod 3" for the destination
width.

It is easier to handle the blorp split buffer offsetting with the
original RGB surface, and do the RGB=>R after this.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
edf3113aed intel/blorp_blit: Adjust blorp surface parameters for split blits
If try_blorp_blit() previously returned that a blit was too large,
shrink_surface_params() will be used to update the surface parameters
for the smaller blit so the blit operation can proceed.

v2:
 * Use double instead of float. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
12e0a6e259 intel/blorp_blit: Split blorp blits if they are too large
We rename do_blorp_blit() to try_blorp_blit(), and add a return error
if the surface size for the blit is too large. Now, do_blorp_blit() is
rewritten to try to split the blit into smaller operations if
try_blorp_blit() fails.

Note: In this commit, try_blorp_blit() will always attempt to blit and
never return an error, which matches the previous behavior. We will
enable the size checking and splitting in a future commit.

The motivation for this splitting is that in some cases when we
flatten an image, it's dimensions grow, and this can then exceed the
programmable hardware limits. An example is w-tiled+MSAA blits.

v2:
 * Use double instead of float. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
b74d4f6ca0 intel/blorp_blit: Create structure for src & dst coordinates
This will be useful for splitting blits into smaller sizes.

We also make the coordinates of type double rather than float. Since
we will be splitting and scaling the coordinates, we might require
extra precision in the calculations.

v2:
 * Use double instead of float. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Nanley Chery
72db1570b4 anv/TODO: Document sampling from HiZ
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-06 14:51:30 -08:00
Jason Ekstrand
eb7b51d62a genxml/gen9: Change the default of MI_SEMAPHORE_WAIT::RegisterPoleMode
We would really like it to be false as that's what you get on hardware that
doesn't have RegisterPoleMode (Sky Lake for example).  While we're at it,
we change it to a boolean.  This fixes dEQP-VK.synchronization.smoke.events
on Broxton.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2016-12-06 11:35:13 -08:00
Jason Ekstrand
c5d664f9dc anv/pipeline: Call nir_lower_constant_initializers
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-12-05 15:40:09 -08:00
Jason Ekstrand
0291bf4db2 Revert "i965: use nir_lower_indirect_derefs() for GLSL"
This reverts commit 9404439a75.  I didn't
intend to push it and it breaks clip and cull distance.
2016-12-05 15:21:20 -08:00
Timothy Arceri
9404439a75 i965: use nir_lower_indirect_derefs() for GLSL
This moves the nir_lower_indirect_derefs() call into
brw_preprocess_nir() so thats is called by both OpenGL and Vulkan
and removes that call to the old GLSL IR pass
lower_variable_index_to_cond_assign()

We want to do this pass in nir to be able to move loop unrolling
to nir.

There is a increase of 1-3 instructions in a small number of shaders,
and 2 Kerbal Space program shaders that increase by 32 instructions.

Shader-db results BDW:

total instructions in shared programs: 8705873 -> 8706194 (0.00%)
instructions in affected programs: 32515 -> 32836 (0.99%)
helped: 3
HURT: 79

total cycles in shared programs: 74618120 -> 74583476 (-0.05%)
cycles in affected programs: 528104 -> 493460 (-6.56%)
helped: 47
HURT: 37

LOST:   2
GAINED: 0
2016-12-05 14:00:35 -08:00
Ilia Mirkin
fda1d0187d anv: expose support for VK_KHR_sampler_mirror_clamp_to_edge
This is already supported in genX_state.c, expose the extension string.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-11-30 20:49:04 -05:00
Jason Ekstrand
27433b26b1 anv/cmd_buffer: Actually use the stencil dimension
In an attempt to fix 3DSTATE_DEPTH_BUFFER for stencil-only cases, I
accidentally kept setting the SurfaceType to 2D in the stencil-only case
thanks to a copy+paste error.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-11-30 17:42:42 -08:00
Ville Syrjälä
676c0cf287 anv: Prefer in-tree headers to out-of-tree headers
Set the include paths to consider in-tree headers before out-of-tree
headers.

Avoids the build failing due to stale headers being present in
$prefix. Previosuly 'make -ki install' or something similar was required
to update the out-of-tree headers to allow the build to succeed.

Also avoids having to rebuild the entire thing after every 'make
install'.

Cc: Rob Clark <robdclark@gmail.com>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-11-30 20:01:00 +02:00
Kristian H. Kristensen
d3d7cab812 aubinator: Add support for enum types
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-29 22:02:49 -08:00
Kristian H. Kristensen
7fc659d8d5 intel/genxml: Fix ksp for INTERFACE_DESCRIPTOR_DATA
This one was split across two dwords as "Kernel Start Pointer" and
"Kernel Start Pointer High", which looks like it works when the driver
only accesses "Kernel Start Pointer". This breaks, of course, with BO
offsets > 4G.

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-29 22:02:49 -08:00
Kristian H. Kristensen
99e573b4e0 intel/genxml: Use enum 3D_Logic_Op_Function where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-29 22:02:49 -08:00
Kristian H. Kristensen
374d19ac00 intel/genxml: Use blend function and factor enums where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-29 22:02:49 -08:00
Kristian H. Kristensen
09fe8ad010 intel/genxml: Use enum 3D_Vertex_Component_Control where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-29 22:02:49 -08:00
Kristian H. Kristensen
54e71e5851 intel/genxml: Use enum 3D_Stencil_Operation where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-29 22:02:49 -08:00
Kristian H. Kristensen
193c1b72e0 intel/genxml: Use enum SURFACE_FORMAT where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-29 22:02:49 -08:00
Kristian H. Kristensen
0799022bf9 intel/genxml: Use enum 3D_Prim_Topo_Type where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-29 22:02:49 -08:00
Kristian H. Kristensen
993babc014 intel/genxml: Use 3D_Compare_Function for gen8+ test functions
When the state fields where shuffled around for gen8, the compare
function enums were downgraded to just uints. Change them to enum
3D_Compare_Function.

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-29 22:02:49 -08:00