Commit graph

28306 commits

Author SHA1 Message Date
Tim Rowley
f833b694cd swr: [rasterizer core] remove all old stats code
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:08:45 -05:00
Tim Rowley
ad153189ec swr: [rasterizer core] viewport array support
Change viewport matrix storage from AOS to SOA to support viewport arrays.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:08:40 -05:00
Tim Rowley
d86e2487a0 swr: [rasterizer jitter] fetch support for offsetting VertexID
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:08:33 -05:00
Tim Rowley
6625fd08db swr: [rasterizer core] fundamentally change how stats work
Add a per draw stats callback to update driver stats.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:08:23 -05:00
Tim Rowley
047493c198 swr: [rasterizer core] add rasterizerSampleCount to PS context
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:08:17 -05:00
Tim Rowley
a83beb936e swr: [rasterizer core] remove cygwin threads.cpp stubs
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:08:11 -05:00
Tim Rowley
29e1c4a8a9 swr: [rasterizer core] allow override of KNOB thread settings
- Remove HYPERTHREADED_FE support
- Add threading info as optional data passed to SwrCreateContext.
  If supplied this data will override any KNOB thread settings.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:08:05 -05:00
Tim Rowley
e0c10306f5 swr: [rasterizer core] add SwrWaitForIdleFE
This is a blocking call that waits until all FE work is complete.
This is useful for waiting for FE work to complete such as for streamout.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:07:59 -05:00
Tim Rowley
8dfaf249cc swr: [rasterizer core] change threadsDone to be a 32-bit value.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:07:53 -05:00
Tim Rowley
6624e01114 swr: [rasterizer core] update trivial accept test conditions
enable/disable raster tile trivial accept test based on scissor enable trait.
Can be optimized further.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:07:47 -05:00
Tim Rowley
7cf187d08a swr: [rasterizer core] improve implementation for SoWriteOffset
1. SoWriteOffset is no longer treated as a stat
2. Added callback from core to update streamout write offset

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:07:40 -05:00
Tim Rowley
8d3b20135e swr: [rasterizer common] make disabled asserts always print (but not break)
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-10 11:07:00 -05:00
Leo Liu
6575ebdc45 vl/rbsp: add a check for emulation prevention three byte
This is the case when the "00 00 03" is very close to the beginning of
nal unit header

v2: move the check to rbsp init

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-08-10 09:52:44 -04:00
Marek Olšák
9c63fd9056 radeonsi: set CB_COLORn_INFO.ROUND_MODE
just do what the register spec says

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-08-10 15:43:36 +02:00
Marek Olšák
667ad9fa3e radeonsi: set CB_COLORn_INFO.SIMPLE_FLOAT
This can help enable some blend optimizations (see the register spec).
Vulkan always sets this.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-08-10 15:43:36 +02:00
Marek Olšák
36057ff12a radeonsi: disallow MIN/MAX blend equations for dual source blending
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-08-10 15:43:36 +02:00
Marek Olšák
947e0614d0 radeonsi: only set dual source blending for MRT0
This is the proper fix for Overlord and Witcher 2 hangs.

The hang condition is that 1 app must write to MRT0 and MRT1 from a pixel
shader while MRT1 is disabled in CB_TARGET_MASK (does this generate
unflushable pixel quads? I don't know), and another app (e.g. Glamor)
must enable dual source blending in both MRT0 and MRT1. The hw gets
confused, which leads to corruption and hangs.

Cc: 12.0 11.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-08-10 15:43:36 +02:00
Trevor Davenport
9a4d5db4d2 st/nine: Fix invalid attempt to use indirect draws.
Since commit 6d7177f01b, radeonsi
would take a different path if info->indirect_params was not
initialized properly.  Nine was not initializating this field.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-08-10 15:02:20 +02:00
Marek Olšák
3f100b77f9 gallium/radeon: use unflushed fences for deferred flushes (v2)
+23% Bioshock Infinite performance.

v2: - use the new fence_finish interface
    - allow deferred fences with multiple contexts
    - clear the ctx pointer after a deferred flush

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-10 01:11:10 +02:00
Marek Olšák
54272e18a6 gallium: add a pipe_context parameter to fence_finish
required by glClientWaitSync (GL 4.5 Core spec) that can optionally flush
the context

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-10 01:11:10 +02:00
Marek Olšák
33a9b4e8a1 gallium/radeon: add HUD queries for mapped VRAM/GTT
mainly for monitoring visible VRAM congestion

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-10 01:11:10 +02:00
Marek Olšák
645d395d9a winsys/radeon: track the amount of mapped memory
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-10 01:11:10 +02:00
Marek Olšák
1e04483c22 winsys/amdgpu: track the amount of mapped memory
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-10 01:11:10 +02:00
Marek Olšák
8276776e64 winsys/amdgpu: don't try to unmap userptr buffers
no app calls this AFAIK

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-10 01:11:10 +02:00
Marek Olšák
ef836c0d04 gallium/radeon: increase the size of the renderer string
Mine is longer than 64 bytes.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-10 01:11:10 +02:00
Marek Olšák
739d526b07 gallium/radeon: implement ARB_clear_texture (v3)
Some ideas copied from Jakob Sinclair's implementation, but the color
clearing is completely different.

v2: remove leftover code, disable conditional rendering
    disable render condition cleanly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-10 01:11:10 +02:00
Marek Olšák
7df15389af gallium/radeon: handle render_condition_enable for clear_rt/ds
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-10 01:10:21 +02:00
Marek Olšák
a909210131 gallium: add render_condition_enable param to clear_render_target/depth_stencil
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-10 01:10:21 +02:00
Mathias Fröhlich
aa920736fe gallium: Add c99_compat.h to u_bitcast.h
We need this for 'inline'.

Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-08-09 21:20:56 +02:00
Mathias Fröhlich
027cbf00f2 util: Move _mesa_fsl/util_last_bit into util/bitscan.h
As requested with the initial creation of util/bitscan.h
now move other bitscan related functions into util.

v2: Split into two patches.

Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-08-09 21:20:46 +02:00
Nicolai Hähnle
e4cb3af524 radeonsi: enable multi-draw related pipe caps
This enables GL_shader_draw_parameters and GL_ARB_indirect_parameters as well
as a properly accelerated implementation of GL_ARB_multi_draw_indirect.

Enabling the feature requires a sufficiently uptodate firmware -- those have
already been released a long time ago, although this does mean that the
feature only works with the amdgpu kernel module, since the radeon module
doesn't have a way to query the firmware version.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-09 15:56:04 +02:00
Nicolai Hähnle
6d7177f01b radeonsi: program additional multi draw parameters
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-09 15:56:04 +02:00
Nicolai Hähnle
b6c71d37c7 radeonsi: program the DRAWID SGPR
Note that for indirect draws, the new MULTI firmware packets are required.

There's also no need to reset last_{start_instance,sh_base_reg}, since
resetting last_base_vertex is sufficient.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-09 15:56:04 +02:00
Nicolai Hähnle
8dbf2a8570 radeonsi: add DRAWID parameter to vertex shaders
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-09 15:56:04 +02:00
Nicolai Hähnle
febb5dbf72 radeonsi: wire up TGSI_SEMANTIC_BASEINSTANCE
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-09 15:56:03 +02:00
Nicolai Hähnle
d34292a77f radeonsi: remove an incorrect assertion
Byte indices don't need any alignment, so remove this assertion (it got moved
into a path where a piglit test hit it during the refactoring of
commit 64ff23a58c).

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-09 15:56:03 +02:00
Nicolai Hähnle
2852dedaa0 radeonsi: flush TC L2 cache for indirect draw data
This fixes a bug when indirect draw data is generated by transform
feedback.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-09 15:56:03 +02:00
Nicolai Hähnle
76c4a3b567 radeonsi/sid: add additional bits for the DRAW_(INDEX)_INDIRECT_MULTI packets
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-09 15:56:03 +02:00
Marek Olšák
06b2fd04f6 ddebug: dump driver states and shaders for apitrace calls
I think this was an oversight when the PIPE_DUMP flags were added.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-09 15:35:42 +02:00
Nicolai Hähnle
96bbb620a5 radeonsi: add has_draw_indirect_multi flag
Prefer to use DRAW_(INDEX)_INDIRECT_MULTI when available in the firmware.

Versions for SI and CI already added as provided by the firmware team, but
keep in mind that they won't currently be used since the radeon kernel module
has no interface to query the firmware version.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-08 12:53:06 +02:00
Nicolai Hähnle
5c343cce0f radeonsi: transpose indirect/index draw dispatch
This allows better code sharing for indirect draw calls.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-08 12:53:04 +02:00
Nicolai Hähnle
64ff23a58c radeonsi: move index buffer calculations in si_emit_draw_packets up
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-08 12:53:02 +02:00
Nicolai Hähnle
cf7d18b75c radeonsi: unify emitting PKT3_SET_BASE for indirect draws
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-08 12:52:59 +02:00
Nicolai Hähnle
e0736c438c winsys/amdgpu: query ME/PFP/CE firmware versions
The radeon kernel module doesn't have the firmware query interface, so the
corresponding values will remain 0.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-08 12:52:41 +02:00
Nicolai Hähnle
7f5a8dc27e radeonsi: move spi_ps_input_addr override outside of the loop
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-08 12:51:32 +02:00
Nicolai Hähnle
287822ee33 radeonsi: drop unnecessary u_pstipple.h include
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-08 12:51:29 +02:00
Nicolai Hähnle
3e4c5693a1 radeonsi: do not pass the return type to buffer_load_const
Overriding it is not allowed anyway, and actually lead to a crash when polygon
stippling was used with monolithic shaders.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-08 12:51:26 +02:00
Marek Olšák
3fb4a9b3b3 Revert "gallium/radeon: count contexts"
This reverts commit b403eb3385.

Not needed.
2016-08-06 17:29:23 +02:00
Marek Olšák
11b1d064a3 radeonsi: add GLSL lit tests
They can only be run manually as described in HOW_TO_RUN.
It should help catch suboptimal code generation.

Some of the tests already fail.

v2: rename the tests to *.glsl,
    fix lit.cfg to find FileCheck

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
2016-08-06 16:11:43 +02:00
Marek Olšák
35942ee8a8 radeonsi: add a standalone compiler amdgcn_glslc
This will be used by GLSL lit tests.

For developers only. It shouldn't be distributable and it doesn't use
the Mesa build system.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 16:11:39 +02:00