Commit graph

194519 commits

Author SHA1 Message Date
Daniel Stone
f5b0699efa ci/angle: Clean up stray open-coded path
Somehow the sed seemed to miss this.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31059>
2024-09-09 12:54:34 +00:00
Daniel Stone
ad6907fb07 util/tests: Reduce load from sparse-array test
Only create 8 threads rather than 16, since otherwise that can hammer
fork a bit too much. Since it creates a bunch of threads, don't try to
run it in parallel with other tests either.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31059>
2024-09-09 12:54:34 +00:00
Daniel Stone
a78539e704 intel/tests: Reduce load from anv_tests
anv_tests tries to create a large number of threads, all of which wait
to be able to execute simultaneously, then launch a reasonable-size
workload.

Under load, cloning each of the 16 threads takes 15ms serially, for a
delay of 240ms before the tests start running; running the test 64
times gives us 15.36s for a single testcase in isolation, assuming that
the bits which aren't forking are free.

To give it the best shot at completing in time, mark it as a
non-parallelisable test (since Meson will also try to parallelise it
out), and also halve the number of runs it attempts. And then give it a
longer timeout so it doesn't fail even in extremis.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31059>
2024-09-09 12:54:34 +00:00
Eric Engestrom
10bc4cc480 docs: Fix linkcheck failures
This job has been failing for a while. Make it not fail.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31059>
2024-09-09 12:54:34 +00:00
Samuel Pitoiset
868272c2e9 radv: disable shaders linking with ESO when nextStage of VS/TES isn't present
For example, if the application wants to create linked shaders with
VS/TCS/TES but the next stage of TES isn't present, the driver would
have to compile shader variants (ie. nextStage could be NONE,TES,GS).

This isn't supported by RADV without re-compiling all shaders twice,
and it's also likely less optimal than compiling unlinked shaders.

This fixes recent CTS
dEQP-VK.shader_object.link.linked_linked_linked_unlinked_unlinked.*

Fixes: 37d7c2172b ("radv: add support for creating/destroying shader objects")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31062>
2024-09-09 11:00:52 +00:00
Pierre-Eric Pelloux-Prayer
316bf3bd8a kopper, dri: remove trace_screen_unwrap
pipe_screen::get_driver_pipe_screen can be used to achieve the same
thing.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30587>
2024-09-09 09:13:51 +00:00
Pierre-Eric Pelloux-Prayer
b7b10b971a radeonsi: add si_screen helper
Add a si_screen cast helper, with 2 purposes:
* correctly cast from pipe_screen to si_screen using get_driver_pipe_screen
* check that the result's type is correct

It's only useful when intending to use pipe_resource::screen as a si_screen.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30587>
2024-09-09 09:13:51 +00:00
Pierre-Eric Pelloux-Prayer
c9806b3595 gallium: add pipe_screen::get_driver_pipe_screen
pipe_resource has a screen pointer, and some drivers expect to be able
to cast it to their specialized version.
This works fine until one of the debug driver is used, because in this
case the driver's pipe_screen subclass can't be obtained with a simple
cast.
To overcome this limitation, this commit introduce a new function with
a default implementation to get the real driver pipe_screen from the
generic interface.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30587>
2024-09-09 09:13:51 +00:00
Pierre-Eric Pelloux-Prayer
06d903920e gallium/ddebug: fix sampler_states handling
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30587>
2024-09-09 09:13:51 +00:00
Pierre-Eric Pelloux-Prayer
4e362f738f gallium/ddebug: implement set_inlinable_constants
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30587>
2024-09-09 09:13:51 +00:00
Pierre-Eric Pelloux-Prayer
746e283fc3 gallium/ddebug: implement modifiers function
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30587>
2024-09-09 09:13:51 +00:00
Vignesh Raman
c6a9a9c3bc ci/deqp-runner: pass EXTRA_CARGO_ARGS
Without EXTRA_CARGO_ARGS='--target armv7-unknown-linux-gnueabihf',
deqp-runner binary was built for aarch64 architecture for arm32
builds and causing below failures on arm32 target,
/usr/bin/deqp-runner: cannot execute binary file: Exec format error

So pass EXTRA_CARGO_ARGS to cargo to fix this.

Fixes: 83d9cfa5 ("ci/deqp-runner: build from git checkout even on linux")
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31071>
2024-09-09 08:26:47 +00:00
Mary Guillemard
51157e7440 docs: Mark timer queries as done on panfrost
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30553>
2024-09-09 09:26:42 +02:00
Mary Guillemard
8ffda8093e panfrost: Implement timer queries
This implement PIPE_CAP_QUERY_TIMESTAMP, PIPE_CAP_QUERY_TIME_ELAPSED and
PIPE_CAP_TIMER_RESOLUTION by using the new uAPI in place.

Effectively, this expose ARB_timer_query, EXT_disjoint_timer_query and
OpenCL profiling on rusticl.

Co-authored-by: Antonino Maniscalco <antonino.maniscalco@collabora.com>
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30553>
2024-09-09 09:16:03 +02:00
Mary Guillemard
dee5223262 panfrost: Move occlusion query allocation to create_query
Also ensure to check if resource allocation failed.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30553>
2024-09-09 09:15:59 +02:00
Mary Guillemard
302127fe9d pan/kmod: Add timestamp uapi support
This adds support for timestamp in kmod based on new uAPI changes.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30553>
2024-09-09 09:15:47 +02:00
Mary Guillemard
76aae6c3da panfrost: Update panthor_drm.h
Update to sync with uAPI changes.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30553>
2024-09-09 09:15:44 +02:00
Mary Guillemard
80fe936be9 panfrost: Update panfrost_drm.h
Update to sync with uAPI changes.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30553>
2024-09-09 09:15:20 +02:00
David Rosca
95d15406c4 radv/video: Don't use multiple tasks for one encode operation
The begin op was sent as one task and encode op as another one.
This doesn't work on VCN2 and older, so just send both ops in same task.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31078>
2024-09-09 06:55:03 +10:00
David Rosca
60c38b9886 radv/video: Don't use op_close in encode
This should only be used on video session destroy, but at that point
we don't have command buffer. RENCODE_IB_OP_CLOSE_SESSION is optional,
so it's okay not using it at all.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31078>
2024-09-09 06:54:47 +10:00
Caio Oliveira
2a5a12cb71 intel/executor: Small fixes to the help message
Add missing @eot to the example.
Reword INTEL_DEBUG=color description.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31076>
2024-09-07 16:32:50 +00:00
Mike Blumenkrantz
1e17f49baf ci: add --pipeline-url to trace update script
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31070>
2024-09-07 12:15:35 +00:00
Mike Blumenkrantz
f944c18fad ci: fix trace update script
this was broken by various things

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31070>
2024-09-07 12:15:35 +00:00
David Rosca
e509139f61 radeonsi/vcn: Add support for H264 8x8 transform on VCN5
Enabling this gives slight increase in quality.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31020>
2024-09-07 04:48:18 +00:00
David Rosca
22d98e35cd radeonsi/vcn: Stop hardcoding values in VCN version overrides
It only makes it more likely to forget updating all functions when
implementing these features and cause issues.
Also fixes H264 constrained_intra_pred on VCN5.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31020>
2024-09-07 04:48:18 +00:00
David Rosca
cd2562117a frontends/va: Parse more H264 PPS for transform_8x8_mode_flag
Also use constrained_intra_pred_flag from pic params.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31020>
2024-09-07 04:48:18 +00:00
Marek Olšák
1537b9355a ac,radeonsi: update comments related to the L2 cache, use "L2", not "TC"
"GL2" is also OK. "TC-compatible" is also OK.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30869>
2024-09-07 01:51:23 +00:00
Marek Olšák
1b94137039 ac/nir/meta: move the "skip compute if no DCC image stores" condition to common
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30869>
2024-09-07 01:51:23 +00:00
Marek Olšák
5250128c6a ac: fix WAVES_PER_SH value for gfx12
not a serious issue because we only use it for PRIME without SDMA IIRC

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30869>
2024-09-07 01:51:23 +00:00
Alyssa Rosenzweig
1753bf599c ci: update traces
🤕

thanks Mike

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
b7542c4390 nir: CSE comparisons in atan2
Same code generated on AGX but simplified NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
7546ae96a7 nir: drop NaN fixup for atan
this existed due to the min/max, per the comment. now that we don't do min/max,
the whole routine is NaN correct so the fixup is pointless.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
ab8547a002 nir: push up abs in atan2 calculation
everybody has abs on fmul, not everyone has abs on bcsel. should help agx and
bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
398e1ad46c nir: fuse ffma for atan range fixup
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
47e7cd268c nir: negate an expression in atan
we're going to fix up the sign immediately anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
5318b8868b nir: simplify atan range reduction fixup
the original version sure is creative.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
87b99d5797 nir: use copysign for atan
this does two things:

* ignores sign of negative numbers which let us play fast and loose later in th
  series
* avoids an expensive fsign instruction in favour of a cheap bitwise op

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
95215a094a nir: extend copysign for no-integer hw
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
0a4a0df283 nir: push down fabs for atan
worse in terms of NIR instruction count but lets the fabs fold easier. (on agx,
which has fabs on comparisons and fmul but not on bcsel. should be no worse if
ISA has fabs on all 3.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
8579375777 nir: simplify atan range reduction
just implement what the comment says, don't be clever. the clever thing is worse
on all architectures i'm familiar with, because the fdiv will turn into
fmul+frcp.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
a32b1a975d nir: correct comment for atan range reduction
the code did not match the comment, blew a sign.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
4fc3e34f2f nir: use Horner's method for atan
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
0c81a29db6 virgl: set no_integers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
a52f606647 svga: set no_integers
for vgpu9 but not 10

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
4b95fb2988 freedreno/a2xx: set no_integers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
531538f678 etnaviv: set no_integers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig
f79f63f8b8 lima: set no_integers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
2024-09-07 00:54:35 +00:00
Boyuan Zhang
8bf7562416 radeonsi/vcn: fix loop filter across slices
PPS header should use pps_loop_filter_across_slices_enabled_flag instead
of slice_loop_filter_across_slices_enabled_flag according to HEVC SPEC.

Slice header should also use pps_loop_filter_across_slices_enabled_flag
as one of the condition to determine if slice flag needs to be present.

V2: Apply pps_loop_filter_across_slices_enabled_flag to loop_filter as well
So modify loop_filter_across_slices_enabled value to be pps one instead

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31064>
2024-09-06 22:48:17 +00:00
Mohamed Ahmed
af15cceff4 nvk: Use stride in the explicit modifier case for linear images
Fixes: f1fdffa1b2 (nvk: Support image creation with modifiers)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31045>
2024-09-06 19:37:09 +00:00
Sil Vilerino
fed08a4ac8 Fix definitions of PIPE_BIND_VIDEO_DECODE/ENCODE_DPB as they conflict with PIPE_BIND_SCANOUT and PIPE_BIND_SHARED
Fixes: f8145fe691 ("pipe: Add PIPE_BIND_VIDEO_DECODE_DPB/PIPE_BIND_VIDEO_ENCODE_DPB")

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31067>
2024-09-06 18:53:11 +00:00