Commit graph

25865 commits

Author SHA1 Message Date
Nicolai Hähnle
f4c8fa4e49 gallium/ddebug: make 'noflush' also affect 'always' mode
This changes the default behavior of 'always' mode to be consistent with
hang detection mode.

I have used this to more easily compare dumped command streams using diff.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-26 09:58:49 -05:00
Nicolai Hähnle
8894b5f008 radeonsi: use llvm.amdgcn.s.barrier instead of llvm.AMDGPU.barrier.local
The new name for the intrinsic was introduced in LLVM r258558.

v2: use ternary operator instead of preprocessor

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-26 09:57:06 -05:00
Nicolai Hähnle
1067e6eb55 radeonsi: add DCC buffer for sampler views on new CS
This fixes a VM fault and possible lockup in high memory pressure situations.

Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-01-25 10:16:12 -05:00
Nicolai Hähnle
0bacbf5b7e radeonsi: emit rw_buffers for tes_shader only if tes_shader present
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:16:08 -05:00
Nicolai Hähnle
2385b253c6 radeonsi: do not set the shader->key for gs copy shaders
The key for a geometry shader would be interpreted as the key for a vertex
shader further down the line, which really doesn't make sense.

This does not affect the contents of shader->key because geometry shaders
don't have any key entries anyway.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:16:05 -05:00
Nicolai Hähnle
46c0ba60c6 radeonsi: si_llvm_emit_vs_epilogue is never used with gs copy shaders
Hence remove the misleading branch on is_gs_copy_shader.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:16:02 -05:00
Nicolai Hähnle
c55b9499d5 radeonsi: move is_gs_copy_shader to si_shader_context
It is only used during shader creation now, so no need to keep it around
afterwards.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:16:00 -05:00
Nicolai Hähnle
a7754ffd31 radeonsi: replace use of is_gs_copy_shader in si_shader_vs
We now have an explicit parameter that contains the same information, and
this will allow us to get rid of is_gs_copy_shader in the si_shader struct.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:15:55 -05:00
Nicolai Hähnle
004fcd4230 radeonsi: ensure that VGT_GS_MODE is sent when necessary
Specifically, when the API switches from using a GS to not using a GS and then
back to using the same GS again, we do not have to re-send all the GS state,
but we do have to send VGT_GS_MODE. So make VGT_GS_MODE consistently be a part
of the VS state.

This fixes a rendering bug in Dolphin, but surely other applications are
affected as well.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93648
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:15:31 -05:00
Nicolai Hähnle
9f89bd69df radeonsi: extract the VGT_GS_MODE calculation into its own function
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:15:08 -05:00
Samuel Pitoiset
429371f22a trace: fix a segfault when tracing indirect draw calls
Like other resources, the indirect draw buffer must be unwrapped.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-24 19:53:53 +01:00
Marek Olšák
e707b9d8ba winsys/amdgpu: optionally use buffer lists with all allocated buffers
Set RADEON_ALL_BOS=1 to use it.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-23 17:01:54 +01:00
Rob Herring
7ee8954753 virgl: enable building on Android
This is just a copy-n-paste and rename of vc4 Android makefiles.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-01-23 12:35:29 +10:00
Marek Olšák
cd9c07e7cd radeonsi: add ETC1 support for Stoney
It's a subset of ETC2. Tested.

For more information, see page 42 and onward:
http://www.graphicshardware.org/previous/www_2007/presentations/strom-etc2-gh07.pdf

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-01-22 22:05:42 +01:00
Marek Olšák
b3bac55621 radeonsi: change LLVM intrinsics for BREV, CLAMP, EX2
Requested by Matt Arsenault.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 22:05:42 +01:00
Marek Olšák
ce1e7784d0 radeonsi: add max waves / SIMD to shader stats (v2)
v2: account for LDS usage in PS
    the limit is per SIMD, not per CU

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 22:05:42 +01:00
Marek Olšák
5944f3d2fc radeonsi: enable late VS allocation (v3)
v2: take the number of CUs into account
v3: change in LS allocation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 22:05:42 +01:00
Marek Olšák
97648229e4 radeonsi: allow using all CUs for tessellation and on-chip GS (v2)
v2: After more discussion with hw teams, the kernel already contains the
    optimal settings allowing us to use all CUs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 22:05:42 +01:00
Nicolai Hähnle
d76bd85c35 Revert "radeonsi: fix discard-only fragment shaders (v2)"
This reverts commit 843855bbf0.

It became redundant due to Marek's earlier pushed 8667a1ae which achieves
the same thing.
2016-01-22 12:40:26 -05:00
Nicolai Hähnle
843855bbf0 radeonsi: fix discard-only fragment shaders (v2)
When a fragment shader is used that has no outputs but does conditional
discard (KILL_IF), all fragments are killed without this patch.

By comparing various register settings, my conclusion is that the exec mask
is either not properly forwarded to the DB by NULL exports or ends up being
unused, at least when there is _only_ a NULL export (the ISA documentation
claims that NULL exports can be used to override a previously exported exec
mask).

Of the various approaches I have tried to work around the problem, this one
seems to be the least invasive one.

v2: take discard by alpha test into account as well

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93761
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-22 11:59:50 -05:00
Marek Olšák
a9d5842ec0 radeonsi: add ETC2 support for Stoney
Tested and working.
2016-01-22 15:36:14 +01:00
Marek Olšák
6f428328d3 radeonsi: implement SAMPLEPOS system value without a constant buffer load
We always get per-sample input position.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
2b66bc87d4 winsys/amdgpu: compute num_good_compute_units correctly
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
0d8e4f958f gallium/radeon: rename max_compute_units -> num_good_compute_units
radeon sets this correctly, but not amdgpu

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
99dfeb01bd radeonsi: disable SPI color outputs the shader doesn't write
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
f6360de8c0 radeonsi: use all SPI color formats
because not using SPI_SHADER_32_ABGR doubles fill rate.

We should also get optimal performance if alpha isn't needed or blending
isn't enabled.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
933e3c4145 radeonsi: use 32_AR for alpha-to-coverage without a color buffer
This avoids the fp16 packing instructions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
f1f0158837 radeonsi: add shader conversion code for all SPI color formats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
e28b8530b9 radeonsi: set CB_SHADER_MASK according to SPI color formats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
8667a1aea2 radeonsi: use SPI_SHADER_COL_FORMAT fields instead of export_16bpc
This does change the behavior slightly:
  If a shader writes COLOR[i] and that color buffer isn't bound,
  the shader will export MRT_NULL instead and discard the IR tree that
  calculates the output. The only exception is alpha-to-coverage, which
  requires an alpha export.

v2: - update a comment about 16BPC
    - account for MRTZ when when fixing alpha-test/kill

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
0446ea9d08 radeonsi: don't enable blending if colormask == 0
most likely useless, but doesn't hurt

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Emil Velikov
f29a772a7e targets/dri: android: use WHOLE static libraries
By using whole static libraries the android buildsystem provides
whole-archive (alike) solution. This means that we don't need to worry
about the order of the static libraries and any reverse, recursive or
circular dependencies that they have between one another.

Without this the linker will discard any unused hunks of one library
and we'll end up with unresolved symbols as those are required by
another static library. This issue has become more prominent with the
introduction of pipe-loader.

Whole static libraries has been used in i915/i965 for a very long
time, so we might do the same.

v2:
 - Better commit message (Ilia)
 - Keep external dependencies as [normal] static libs (Mauro)

Cc: mesa-stable@lists.freedesktop.org
Cc: Mauro Rossi <issor.oruam@gmail.com>
Reported-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-01-22 11:55:34 +00:00
cstout
13b87e02b9 freedreno/a4xx: Add support for adreno 430
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-21 17:20:11 -05:00
Christian Gmeiner
66672e791c freedreno: make opc array static const
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-21 17:20:11 -05:00
Rob Clark
bc1a37378c freedreno: implement emit_string_marker
Writes string to cmdstream in payload of a no-op packet.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-21 17:20:11 -05:00
Rob Clark
d6408372eb gallium: add GREMEDY_string_marker
Since the GREMEDY extensions are normally only exposed by the gremedy
debugger (and could possibly trigger debug paths in the app), we don't
expose the extension by default, but instead only with
ST_DEBUG=gremedy.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-21 17:19:56 -05:00
Grazvydas Ignotas
0153ff8379 r600g: don't leak driver const buffers
The buffers are referenced from r600_update_driver_const_buffers()
 -> r600_set_constant_buffer() -> u_upload_data(), but nothing
ever releases the reference. Similar case with driver_consts.
Found using valgrind.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-21 15:36:24 -05:00
Ilia Mirkin
daa0fd7843 nv50/ir: 64-bit splitting fixes
Take reading shader outputs into account, and use setFlagsDef for the
carry since we rely on having i->flagsDef being set.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-20 19:37:34 -05:00
Ilia Mirkin
c0b66d96d7 gk110/ir: allow carry to be set/read by imad
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-20 19:37:34 -05:00
Ilia Mirkin
73c9ca7544 gm107/ir: add carry emission to LOP and IADD
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-20 19:37:34 -05:00
Ilia Mirkin
71a489633b gm107/ir: add ATOM and CCTL support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-20 19:37:34 -05:00
Ilia Mirkin
57b0025814 gm107/ir: set LD/ST address width bit
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-20 19:37:34 -05:00
Ilia Mirkin
2e533ab74b gk110/ir: fix double-wide vm address 2016-01-20 19:37:34 -05:00
Ilia Mirkin
8c2dfe05c5 gk110/ir: add OP_CCTL handling 2016-01-20 19:37:33 -05:00
Ilia Mirkin
7d9a97d6be gk110/ir: add atomic op emission, fix gmem loads
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-20 19:37:33 -05:00
Roland Scheidegger
dc8b9bd0aa llvmpipe: warn about illegal use of objects in different contexts
Doing that is clearly a bug. We can't quite assert as st/mesa may hit this,
but increase at least visibility of it a bit.
(For the non-refcounted objects it would be illegal too, but we can't detect
that unless we'd store the context ourselves. Plus, those don't tend to cause
random crashes at context or object destruction time... So just sampler views,
surfaces and so targets for now.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-21 00:09:55 +01:00
Roland Scheidegger
e925ec8811 llvmpipe,i915: add back NEW_RASTERIZER dependency when computing vertex info
I removed this mistakenly in 2dbc20e456. I
actually thought it should not be necessary and a piglit run didn't show
any differences, but this shouldn't have been in there.
draw_prepare_shader_outputs() is in fact dependent on NEW_RASTERIZER.
The new polygon-mode-facing test indeed shows why this is necessary, there's
lots of invalid reads and writes with valgrind (also crashes without
valgrind), because the pre-pipeline vertex size doesn't match the
post-pipeline vertex size (note this won't help much with stages which don't
have the prepare hook which can grow the vertex size, in particular the wide
point stage, but this isn't used by llvmpipe). The test still won't pass, of
course, but it is only usage of uninitialized values now, which is much
less dangerous...
(Albeit I'm pretty sure for i915 it really is not needed anymore as it
doesn't care about the extra outputs and doesn't call
draw_prepare_shader_outputs().)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-21 00:09:55 +01:00
Ilia Mirkin
dc3ac418bf nv50/ir: don't flip SHL(ADD) into ADD(SHL) if ADD sources have modifiers
Fixes: 31fde8fa (nv50/ir: flip shl(add, imm) into add(shl, imm))
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-20 18:03:36 -05:00
Ilia Mirkin
3a63576168 gk110/ir: fix load from shared memory
It was accidentally using the store opcode.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-20 17:16:09 -05:00
Ilia Mirkin
9f23007a7a gk110/ir: add partial BAR support
This is enough for the plain TGSI BARRIER implementation.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-20 17:16:09 -05:00