Commit graph

178412 commits

Author SHA1 Message Date
Alyssa Rosenzweig
f4042afd57 nir: Add layer_id_written_agx sysval
We'll implement layer ID reads in the frag shader with a varying read, but if
the VS doesn't write the varying we need to return 0 per the spec. Add a sysval
to detect that case so we can handle it at runtime without keys.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00
Alyssa Rosenzweig
d83d24e96a agx: Insert jmp_exec_none instructions
With the exception of the backwards branch for loops, all the control flow we
insert during instruction selection just predicates instructions rather than
actually jumping around. That means, for example, we execute both sides of the
if even for a uniform condition! That's inefficient. The solution is insert
jmp_exec_none instructions after control flow in order to skip unexecuted
regions, which is much faster than predicating them out. However, jmp_exec_none
is costly in itself, so we need to use a heuristic to determine when it's
actually beneficial.

This uses a very simple heuristic for this purpose. However, it is a massive
performance speed-up for Dolphin uber shaders: 39fps -> 67fps at 2x resolution.
Nearly a doubling of performance!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00
Alyssa Rosenzweig
79c4d4213c agx: Add agx_prev_block helper
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00
Alyssa Rosenzweig
dd6106c8bd agx: Add jumps to block ends
jmp_exec_none variant that jumps to the last instruction of the target block,
rather than the beginning. This is convenient for skipping over elses, while
still executing the block-final pop_exec instruction. Similarly for skipping
over loop bodies while still executing the block-final pop_exec, after break
instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00
Alyssa Rosenzweig
22ab505a3d agx: Augment if/else/while_cmp with a target
Add an optional pointer to a target block for these instructions. This does NOT
act like a logical branch, and does NOT get added to the logical control flow.
It is ignored wholesale until after RA, when physical edges may be inserted by a
pass we add later in this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00
Alyssa Rosenzweig
9a894c9a33 agx: Set PIPE_SHADER_CAP_CONT_SUPPORTED
So we get adequate testing of continues, rather than lowering them in GLSL. We
don't really /want/ to see continues but lowering them away will just make them
harder to test... and besides, we should be optimizing them in NIR (not GLSL) so
we can get the win on Vulkan too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00
Alyssa Rosenzweig
d05657e0d6 agx: Hoist sample_mask/zs_emit
Although this is well-motivated, perf effect seems to be neglible for Dolphin.
It does prevent the scheduler from making things worse by sinking these
instructions though, so as a way to prevent future problems this seems sensible.

The kind of problem this affects (late discard) isn't modelled in shader-db.
Nevertheless, nothing concerning there:

   total instructions in shared programs: 1756699 -> 1756722 (<.01%)
   instructions in affected programs: 10106 -> 10129 (0.23%)
   helped: 21
   HURT: 41
   Inconclusive result (value mean confidence interval includes 0).

   total bytes in shared programs: 11525404 -> 11525452 (<.01%)
   bytes in affected programs: 72900 -> 72948 (0.07%)
   helped: 27
   HURT: 41
   Inconclusive result (value mean confidence interval includes 0).

   total halfregs in shared programs: 483394 -> 483286 (-0.02%)
   halfregs in affected programs: 4945 -> 4837 (-2.18%)
   helped: 88
   HURT: 78
   Inconclusive result (value mean confidence interval includes 0).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00
Alyssa Rosenzweig
0d8362b842 agx: Align the reg file for 256-bit vectors
This fixes live range splitting with 3D textureGrad(), which involves vectors
larger than the natural 128-bit maximum and hence requires special handling.
Fixes this assert with a combination of debug flags and new patches:

   unsigned int find_best_region_to_evict(struct ra_ctx *, unsigned int,
   unsigned int *, unsigned int *):
   Assertion `(rctx->bound % size) == 0 && "register file size must be aligned
   to the maximum vector size"' failed

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00
Alyssa Rosenzweig
cb14cddfa5 asahi: Clamp index buffer extent to what's read
This makes for cleaner agxdecodes, I think this matches what I've seen on the
macOS side but I might be misremembering. Certainly shouldn't hurt.

This only applies for direct draws.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00
Friedrich Vock
2be9b66cdd radv: Fix check in insert_block
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25496>
2023-10-01 13:11:50 +02:00
Friedrich Vock
a0fba17311 radv: Initialize shader freelist on allocation
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25496>
2023-10-01 13:11:43 +02:00
Vitaliy Triang3l Kuzmin
a43ee1ca50 r600: Replace R600_BIG_ENDIAN with UTIL_ARCH_BIG_ENDIAN
In particular, removes the dependency of r600_formats.h on r600_pipe.h so
it can be shared between Gallium and Vulkan.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24513>
2023-10-01 09:25:50 +00:00
Marek Olšák
43e7285069 winsys/amdgpu: pad gfx and compute IBs with a single NOP packet
to minimize CP overhead

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25043>
2023-10-01 08:45:22 +00:00
Marek Olšák
4f660f9937 ac/gpu_info: pad IBs according to ib_size_alignment
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25043>
2023-10-01 08:45:22 +00:00
Marek Olšák
b6f435888b ac/gpu_info: replace ib_alignment with per-IP IB base and size alignments
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25043>
2023-10-01 08:45:22 +00:00
Eric Engestrom
276caddbd9 ci/deqp-runner: restore exit-on-error after getting deqp-runner's exit code
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24738>
2023-10-01 02:00:50 +00:00
Eric Engestrom
f8326d0950 ci/deqp-runner: fix indentation
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24738>
2023-10-01 02:00:50 +00:00
Marek Olšák
6b29c16db8 amd: rename GFX110x to NAVI31-33
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25492>
2023-09-30 23:08:47 +00:00
Marek Olšák
c7e08acd12 ac/llvm: fix flat PS input corruption
Fixes: 0a54fbb5b4 - radeonsi/gfx11: interp changes for 32bit

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25492>
2023-09-30 23:08:47 +00:00
Marek Olšák
d50cc2e0cf ac/gpu_info: don't align IBs to the GL2 cache line size
PAL doesn't do it. If drivers want IBs not to share cache lines with other buffers,
they should align the size manually.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25492>
2023-09-30 23:08:46 +00:00
Marek Olšák
2d928c7fee ac/llvm: set !fpmath 3.0 for llvm.sqrt
LLVM will be changed to increase precision with additional instructions,
which we don't want.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25492>
2023-09-30 23:08:46 +00:00
Marek Olšák
476529a692 ac/perfcounter: remove a bogus assert to fix an assertion failure on gfx11
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25485>
2023-09-30 22:23:04 +00:00
Eric Engestrom
2e100bd69b ci: move shader-db clone/build into its own script
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24504>
2023-09-30 14:55:09 +00:00
Eric Engestrom
e7c0971b4f ci: drop unused shader-db clone + build from fedora image
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24504>
2023-09-30 14:55:09 +00:00
Eric Engestrom
16201d5896 ci: drop unused shader-db clone + build from alpine image
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24504>
2023-09-30 14:55:09 +00:00
Konstantin Seurer
ca92a10800 radv: Do not sync after radv_update_buffer_cp
WR_CONFIRM is set.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24846>
2023-09-30 11:49:14 +00:00
Konstantin Seurer
3fd0ff21e0 radv: Merge the sync_data and header initialization
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24846>
2023-09-30 11:49:14 +00:00
Konstantin Seurer
b3c43d6865 radv/bvh/ploc: Load child bounds from LDS
The bounds are already in LDS so there is no need to load them from
VRAM.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24846>
2023-09-30 11:49:14 +00:00
Eric Engestrom
8a80a3607c docs: document the merging process and what is allowed or not
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25117>
2023-09-30 11:42:32 +00:00
Cong Liu
e7d393b1d7 virgl:Fix ITEM_CPY macro pointer copy bug
The ITEM_CPY macro uses the memcpy function to copy the item variable.
When item is a pointer, the memcpy function will copy the value of the
pointer, not the address that the pointer points to.

Signed-off-by: Cong Liu <liucong2@kylinos.cn>
Reviewerd-by: Feng Jiang <jiangfeng@kylinos.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25453>
2023-09-30 03:01:21 +00:00
Guilherme Gallo
6de10c3585 ci/anv: Catch some flakes
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25469>
2023-09-29 17:27:49 -03:00
Guilherme Gallo
6217540eda ci/zink: Found some flakes
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25469>
2023-09-29 17:27:49 -03:00
Guilherme Gallo
2d66147376 ci/freedreno: Add a new flake
KHR-GLES31.core.compute_shader.simple-compute-shared_context resulted in
an UnexpectedPass during execution of the job
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/49445812

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25469>
2023-09-29 17:27:49 -03:00
Guilherme Gallo
8e2a049cc6 ci/radeonsi: Update flake list
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25469>
2023-09-29 17:27:49 -03:00
Mike Blumenkrantz
a524f6b5d4 radv: fix external handle type queries for dmabuf/fd
the intent of the VkExternalMemoryProperties API is that all compatible
handle types are returned, not just the type being queried. these two
types are compatible, so return both when both are supported

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25474>
2023-09-29 18:57:13 +00:00
Rhys Perry
6518d09601 aco: don't combine DPP into v_cmpx
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25471>
2023-09-29 18:23:21 +00:00
Rhys Perry
ea633c128c aco/optimizer_postRA: don't combine DPP across exec on GFX8/9
GFX8/9 seem to use FI=0 behaviour.

fossil-db (vega10):
Totals from 1 (0.00% of 63053) affected shaders:
Instrs: 542 -> 570 (+5.17%)
CodeSize: 2928 -> 3040 (+3.83%)
Latency: 2087 -> 2118 (+1.49%)
InvThroughput: 1103 -> 1143 (+3.63%)

Affected shader is from Cyberpunk 2077 fossil.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Cc: 23.2 <mesa-stable>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9784
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25471>
2023-09-29 18:23:21 +00:00
Helen Koike
fa884141dc ci/ci_run_n_monitor: add docs for multiple targets
clarify how multiple targets can be used with the pipe character.

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25472>
2023-09-29 09:50:53 -03:00
Lionel Landwerlin
a25f96c00c intel/fs: switch from SIMD 1 to 8 instructions surface/sampler rematerialization
SIMD1 instructions are problematic because they are considered partial
writes. This increases the liveness of the destination register
written by those instructions. To workaround this we use UNDEF
instructions to bound the liveness of the register. But this causing
other issues like in this case :

  undef(1) vgrf2
  mov(1)   vgrf2, u4.0
  add(1)   vgrf3, vgrf2.0, 64UD

In this case the copy propagation pass in unable to see that vgrf2 in
the add() instruction can be replaced with the uniform u4.0.

To fix this problem, we switch NoMask SIMD8 instructions that cover
the entire register. We can drop the UNDEF instructions and now copy
propagation can do its job.

Good results on 2 apps :

Cyberpunk 2077 :

  Totals from 7258 (68.80% of 10549) affected shaders:
  Instrs: 6332210 -> 6073833 (-4.08%); split: -4.11%, +0.03%
  Cycles: 130667501 -> 127351268 (-2.54%); split: -3.12%, +0.58%
  Subgroup size: 90320 -> 90400 (+0.09%)
  Spill count: 90 -> 68 (-24.44%)
  Fill count: 82 -> 64 (-21.95%)
  Scratch Memory Size: 8192 -> 6144 (-25.00%)
  Max live registers: 385464 -> 375152 (-2.68%)
  Max dispatch width: 64336 -> 64424 (+0.14%); split: +0.96%, -0.82%

  Gaining 60 SIMD16/SIMD32 shaders, loosing 33

Strange Brigade :

  Totals from 2137 (53.12% of 4023) affected shaders:
  Instrs: 1544031 -> 1457544 (-5.60%); split: -5.60%, +0.00%
  Cycles: 22292564 -> 21868978 (-1.90%); split: -2.43%, +0.53%
  Subgroup size: 25328 -> 25344 (+0.06%)
  Max live registers: 113716 -> 111214 (-2.20%)
  Max dispatch width: 17232 -> 18608 (+7.99%); split: +8.36%, -0.37%

  Gaining 138 SIMD16/SIMD32 shaders, loosing 4

On app slightly negatively affected :

Dota2 :

  Totals from 232 (14.73% of 1575) affected shaders:
  Instrs: 30029 -> 28194 (-6.11%)
  Cycles: 385155 -> 371422 (-3.57%); split: -3.59%, +0.02%
  Max live registers: 6792 -> 6780 (-0.18%)
  Max dispatch width: 2256 -> 2160 (-4.26%)

  Loosing 6 SIMD32 shaders

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24554>
2023-09-29 10:46:47 +00:00
Lionel Landwerlin
d28f42f85d intel/fs: handle add3 in surface/sampler rematerialization
Some recent NIR changes started generated those instructions. We need
to handle them to be able to rematerialize.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24554>
2023-09-29 10:46:47 +00:00
Lionel Landwerlin
05fd418e8b intel/fs: handle ishl in surface/sampler rematerialization
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24554>
2023-09-29 10:46:47 +00:00
Samuel Pitoiset
83cad95358 radv: emit missing PA_{SC,SU}_LINE_STIPPLE_xxx regs in gfx preamble
Ported from RadeonSI and PAL.
This might fix the line stipple flakes in CI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25428>
2023-09-29 07:50:46 +00:00
Samuel Pitoiset
a9945216ba radv: fix COMPUTE_SHADER_INVOCATIONS query on compute queue
The VA needs to be adjusted, otherwise the hw always writes at offset 0.

This fixes dEQP-VK.query_pool.statistics_query.*_cq.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25406>
2023-09-29 07:16:44 +00:00
Samuel Pitoiset
c1b916ccb9 radv: re-enable DCC with mipmaps on GFX11
This is now fixed.

Hi-Fi Rush, Sonic Frontiers and Hogwarts Legacy were known broken games.

I personally reproduced the issue with Hi-Fi Rush which has been fixed
since e6735409ee ("radv: disable DCC with signedness reinterpretation
on GFX11"). I also tested Sonic Frontiers which has been fixed since
52b6886992 ("amd: update addrlib"). I didn't check Hogwarts Legacy but
I think it was also fixed by e6735409ee.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25435>
2023-09-29 06:54:42 +00:00
Caio Oliveira
80a1896539 compiler/types: Add void parameter to ensure these are valid C prototypes
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>
2023-09-28 22:43:45 +00:00
Caio Oliveira
cc1fac52da compiler/types: Spell struct and enum in type names
This is a preparation for moving compiler/types from C++ to C.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>
2023-09-28 22:43:45 +00:00
Caio Oliveira
95465b813f compiler/types: Use C compatible cast syntax
This is a preparation for moving compiler/types from C++ to C.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>
2023-09-28 22:43:45 +00:00
Caio Oliveira
0158057bd0 compiler/types: Remove use of auto
This is a preparation for moving compiler/types from C++ to C.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>
2023-09-28 22:43:45 +00:00
Caio Oliveira
4a8918f7e1 compiler/types: Remove use of references
This is a preparation for moving compiler/types from C++ to C.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>
2023-09-28 22:43:45 +00:00
Caio Oliveira
57819effc1 compiler/types: Remove use of new/delete
This is a preparation for moving compiler/types from C++ to C.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25445>
2023-09-28 22:43:45 +00:00