For now, we're just using this in place of IAdd3x for 64-bit adds. IADD3
with carry flags is supported on SM50, but it works completely
differently from SM75. Longer-term we'll probably want to emit this in
all of the places that we're currently using IADD3.
Also need to hook the carry register up to calc_deps, but for now I'm
just using NAK_DEBUG=serial.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
Rename it to set_src_i20 and fix the assert to allow negative signed
values. Also, add a new set_src_f20 helper with the correct semantics
for float immediates. Finally, get rid of some bogus shifting in the
ALU code.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
Only encode some instructions.
some TODO:
- SM50 specific legalizer
- Cleaner ALU encoding (there is multiple form of encoding depending of
the instruction)
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
Bindings are not necessarily globally unique, and even the location
where we were trying to read the binding value out of is a union, so
we could be trying to compare binding values against data for other
arg types.
Instead, use the arg metadata offset, which is globally unique and
outside of the union.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26555>
Since nir_opt_algebraic runs on its own results, if the driver doesn't
have [su]dot_4x8_[ui]add then the [su]dot_4x8_[ui]add lowering rules
will kick in and lower that to what we had originally.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26533>
With this commit, NAK now takes on a more Cargo-like structure with
things split better into crates:
- bitview/
- lib.rs // Formerly bitview.rs
- nak/
- lib.rs // Only pulls stuff into the module
- api.rs // Formerly nak.rs
- ...
- nvfuzz/
- main.rs // Formerly nvfuzz.rs
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26546>
Batch bos are always allocated with ANV_BO_ALLOC_HOST_CACHED_COHERENT
so there is no need to do cflush calls.
But if we ever decide to change that anv_bo_needs_host_cache_flush()
will make sure cflush is called.
Outside of batch bos, this patch is also removing the
intel_flush_range() call from anv_QueuePresentKHR because
device->debug_frame_desc is offset of workaround_bo that is also
allocated as ANV_BO_ALLOC_HOST_COHERENT.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>
In platforms with LLC we can promote all bos to cached+coherent
without any performance penality.
On the up side CPU reads can hit cache this way.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>
