Commit graph

169770 commits

Author SHA1 Message Date
Alyssa Rosenzweig
efaffcfbd4 nir: Add more system values for lowering XFB
Add more system values for XFB. This should be good enough for lowering GL3.1 +
transform_feedback2 + transform_feedback3. More will probably be needed for
geom/tess but that will be easier to work with when I'm actually bringing up
geom/tess. At any rate, we're splitting out XFB from the rasterization pipeline
and since XFB happens only in the last shader pre-rasterization stage, VS+XFB is
an orthogonal problem from e.g. VS+GS+XFB. Yeah, the combinatorics suck.

These will be used by Asahi, and hopefully eventually Panfrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22123>
2023-04-13 18:04:25 +00:00
Alyssa Rosenzweig
947a7590c7 d3d12: Use u_default_get_sample_position
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22383>
2023-04-13 15:40:54 +00:00
Alyssa Rosenzweig
07e83f5819 freedreno: Use u_default_get_sample_position
Verified by hand to produce the same results.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22383>
2023-04-13 15:40:54 +00:00
Alyssa Rosenzweig
71cfe8fb60 panfrost: Use u_default_get_sample_position
The Mali sample positions are the standard sample positions.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22383>
2023-04-13 15:40:54 +00:00
Alyssa Rosenzweig
43f9903d0c zink: Use u_default_get_sample_position
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22383>
2023-04-13 15:40:54 +00:00
Alyssa Rosenzweig
6b211e9b43 gallium: Add u_default_get_sample_position
ctx->get_sample_position doesn't change what it returns based on the programmed
positions, it's just supposed to return the defaults. For most (all?) hardware,
those are the Vulkan standard sample positions. In bf9a1e0a4b ("zink: add a
pipe_context::get_sample_position hook"), Mike wondered why there wasn't a
common implementation. So here's one to fix that :~)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22383>
2023-04-13 15:40:54 +00:00
José Roberto de Souza
6124f8f371 iris: Set priority to Xe engines
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22172>
2023-04-13 14:58:55 +00:00
José Roberto de Souza
a564baf6e7 iris: Implement batch_check_for_reset() in Xe kmd backend
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22172>
2023-04-13 14:58:55 +00:00
José Roberto de Souza
17c7eb1d4f iris: Create, destroy and replace Xe engines
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22172>
2023-04-13 14:58:55 +00:00
José Roberto de Souza
35d6e830c7 iris: Move iris_batch i915 specific variables to union
Saves some bytes when Xe kmd fields are added and makes easier to
spot places that are misusing i915 variables.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22172>
2023-04-13 14:58:55 +00:00
José Roberto de Souza
b6cf4001d3 iris: Initialize batch screen in iris_init_batch()
The comment to initialize screen earlier not valid anymore so we can
initialize it with the rest of batch fields.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22172>
2023-04-13 14:58:55 +00:00
José Roberto de Souza
35a547430e iris: Move i915 batch destroy logic to iris_i915_destroy_batch()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22172>
2023-04-13 14:58:55 +00:00
xurui
f66e6b671c zink: Some return values of malloc should be checked
Signed-off-by: xurui <xurui@kylinos.cn>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22328>
2023-04-13 13:40:22 +00:00
Samuel Pitoiset
0b4e7491f3 radv: fix detecting FMASK_DECOMPRESS/DCC_DECOMPRESS meta pipelines
With the on_demand shaders feature, meta pipelines are only created
when they are used, otherwise they are NULL. Though, inside secondary
cmdbuffers, the graphics pipeline might be also NULL. In this specific
case, radv_is_{dcc,fmask}_decompress_pipeline() would return
TRUE because these pipelines are NULL too...

This fixes flakes with tests that use secondary cmdbuffers with
TC-compat images.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22440>
2023-04-13 09:00:38 +00:00
Eric Engestrom
8f024cdd4d docs: reset new_features.txt
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22455>
2023-04-13 08:45:17 +00:00
Eric Engestrom
4aab6bd456 VERSION: bump to 23.2
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22455>
2023-04-13 08:45:17 +00:00
Qiang Yu
45826e42c5 ac,aco: move gfx10 ngg prim count zero workaround to nir
To simplify both llvm and aco backend and remove unnecessary
workaround code where prim count is known to be not zero.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22381>
2023-04-13 08:12:03 +00:00
Tapani Pälli
b967cbba57 intel/compiler: use intel_needs_workaround for Wa_14012437816
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22437>
2023-04-13 07:33:50 +00:00
Tapani Pälli
ccf16693e1 intel/fs: use intel_needs_workaround for Wa_22013689345
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22437>
2023-04-13 07:33:50 +00:00
Eric Engestrom
1a9727a81e ci/rustfmt: make sure to only check each file once
rustfmt has some magic that follows files (I'm guessing), making files get
checked multiple times with `*.rs`, so let's limit ourselves to `lib.rs`.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22321>
2023-04-13 05:56:53 +00:00
Tatsuyuki Ishi
36fd2bbd98 ci/android: Make armv8's arch aarch64 instead of arm.
Per [1], arm is for 32-bit.

For an upcoming change, we need to detect AArch64 specifically.
Specifying arm in the cross file will result in the wrong build script
behavior.

[1]: https://mesonbuild.com/Reference-tables.html#cpu-families

Reviewed-by: Helen Koike <helen.koike@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22418>
2023-04-13 04:28:29 +00:00
Mike Blumenkrantz
1a63ccc9aa zink: remove a fixed validation error for ci
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22453>
2023-04-13 04:10:32 +00:00
Karol Herbst
55c9356d29 rusticl/program: rework source code tracking
For the CL spec it really matters how a program object was created. We
never really cared all that much, but it didn't support the corner case of
having an empty string as the OpenCL C source code.

Enums feel like the more Rust way to do this kind of stuff anyway.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22280>
2023-04-13 02:54:21 +00:00
Karol Herbst
6d7b705125 rusticl/program: extract common code of compile and build
The code wasn't all the same, but the build version was wrong, e.g. the
compile flags specified need to be stored even on error.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22280>
2023-04-13 02:54:21 +00:00
Karol Herbst
d7e9b4ef5b rusticl/program: validate the SPIR-V when created from IL
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8771
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22280>
2023-04-13 02:54:21 +00:00
Karol Herbst
8fcfc51dad clc: add clc_validate_spirv
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22280>
2023-04-13 02:54:21 +00:00
Karol Herbst
ab032f4bfd rusticl/program: make IL programs look closer to CLC ones
We want to validate the actual passed in SPIR-V, but we can only report
errors back on build/compile time. So instead of storing the initial IL
in the devices `ProgramBuild` objects, just store it on the Program
instead. This also simplifies setting spec constants as this is only valid
on program directly created from IL and not e.g. linked ones.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22280>
2023-04-13 02:54:21 +00:00
Karol Herbst
ca1e9917a9 rusticl/program: allow dumping compilation logs through RUSTICL_DEBUG
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22280>
2023-04-13 02:54:21 +00:00
Karol Herbst
22808d542b rusticl/platform: move device initialization to the platform
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22280>
2023-04-13 02:54:21 +00:00
Karol Herbst
53025688bb rusticl/platform: move getter into the type
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22280>
2023-04-13 02:54:21 +00:00
Karol Herbst
3e59a2860e rusticl/platform: rename _cl_platform_id to Platform
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22280>
2023-04-13 02:54:21 +00:00
Karol Herbst
11250d7a9e rusticl: split platform into core and api parts
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22280>
2023-04-13 02:54:20 +00:00
Samuel Pitoiset
3320eee877 radv: cleanup after splitting radv_pipeline.c
I moved to many things to radv_pipeline_graphics.c without checking.

Fixes: 7783b7f697 ("radv: split radv_pipeline.c into radv_pipeline_{compute,graphics}.c")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22441>
2023-04-13 02:21:44 +00:00
Vitaliy Triang3l Kuzmin
30d141ba63 r600: Alpha to coverage dithering on Evergreen+
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22384>
2023-04-13 02:07:52 +00:00
Alyssa Rosenzweig
7a7d374ac3 pan/decode: Print compute job payloads
Noticed while debugging OpenCL. I think this was fallout from the CSF decode
rework?

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22228>
2023-04-13 01:49:33 +00:00
Alyssa Rosenzweig
de01ae120d panfrost: Allocate shared memory in OpenCL
In OpenCL, we can have no shader-defined shared memory but some dispatch-time
variable memory. This is not reflected in ss->info.wls_size, so check the right
variable instead so we allocate the appropriate memory.

Fixes page faults accessing shared memory with Rusticl, e.g. in the vstore_local
test.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22228>
2023-04-13 01:49:33 +00:00
Alyssa Rosenzweig
2f2738dc90 pan/bi: Use nir_lower_mem_access_bit_sizes
OpenCL can generate large loads and stores that we can't support, so we need to
lower. We can load/store up to 128-bits in a single go. We currently only handle
up to 32-bit components in the load and no more than vec4, so we split up
accordingly.

It's not clear to me what the requirements are for alignment on Valhall, so we
conservatively generate aligned access, at worst there's a performance penalty
in those cases. I think unaligned access is suppoerted, but likely with a
performance penalty of its own? So in the absence of hard data otherwise, let's
just use natural alignment.

Oddly, this shaves off a tiny bit of ALU in a few compute shaders on Valhall,
all in gfxbench. Seems to just be noise from the RA lottery.

total instructions in shared programs: 2686768 -> 2686756 (<.01%)
instructions in affected programs: 584 -> 572 (-2.05%)
helped: 6
HURT: 0
Instructions are helped.

total cvt in shared programs: 14644.33 -> 14644.14 (<.01%)
cvt in affected programs: 5.77 -> 5.58 (-3.25%)
helped: 6
HURT: 0

total quadwords in shared programs: 1455320 -> 1455312 (<.01%)
quadwords in affected programs: 56 -> 48 (-14.29%)
helped: 1
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22228>
2023-04-13 01:49:33 +00:00
Alyssa Rosenzweig
934b0f1add pan/bi: Respect swizzles for more vector ops
We need to respect the ALU swizzle, this takes a vector. Fixes incorrect
pack_64_2x32 translation hit when wiring up lower_mem_access_bit_sizes for
OpenCL.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22228>
2023-04-13 01:49:33 +00:00
Alyssa Rosenzweig
d00d2ae701 pan/bi: Lower swizzles for 8-bit CSEL
With OpenCL we can generate stuff like CSEL.u32.eq r0.b0000, we need to handle
it when lowering swizzles.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22228>
2023-04-13 01:49:33 +00:00
Lionel Landwerlin
66edd030ab anv: add utrace tracking of frame boundaries
Based on vkQueuePresentKHR calls. It just helps spotting the beginning
end of a frame in perfetto when apps are using 3/4 command buffers per
frame.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22276>
2023-04-13 01:14:38 +00:00
Lionel Landwerlin
da6842007f intel/ds: add a new timeline row for frames
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22276>
2023-04-13 01:14:38 +00:00
Lionel Landwerlin
68bba1539f anv: exclude performance queries from blorp clears
The query buffer contains a batch to implement the multi pass
replay/accumulation of results. So we can't clear it with a memset.

An optimization for later would be to move the batches to the very end
of the query buffer so we can clear the query data without touching
the batches.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4dc7256bf9 ("anv: reset query pools using blorp")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22421>
2023-04-13 00:44:29 +00:00
Timur Kristóf
7036d1a155 ac/nir/ngg: Don't store primitive IDs from culled primitives.
Primitive export used the gs_accepted variable after culling,
so we overwrote this variable after vertex compaction to make
sure not to hang the GPU.

This had an unintended side effect when storing the primitive ID
to LDS on GS threads: the LDS store was done even on threads whose
triangle was culled; potentially causing issues.

As a fix, create a separate boolean variable that remembers
which invocations need to export a primitive; and don't store
the primitive ID to LDS when gs_accepted is false.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8805
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22424>
2023-04-12 23:55:37 +00:00
Ruijing Dong
31c4087cb3 frontends/va: disable skip_frame_enable in vaapi interface.
skip_frame_enable is for preventing overshooting in some cases,
however the tests in FW were broken, and the output result shows
the functionality has not completed yet, which is the reason
this should be disabled at the moment until it has been fully
verified.

Cc: mesa-stable
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8178

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22428>
2023-04-12 23:40:23 +00:00
Oleksii Bozhenko
8976d8280f wsi: remove get_sorted_vk_formats duplication
Fixes: 37a8b2d12e
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8727

Signed-off-by: Oleksii Bozhenko oleksii.bozhenko@globallogic.com

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22337>
2023-04-12 22:07:32 +00:00
Oleksii Bozhenko
53106c3a4f wsi: add rgb_component_bits_are_equal
Signed-off-by: Oleksii Bozhenko oleksii.bozhenko@globallogic.com

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22337>
2023-04-12 22:07:32 +00:00
Mike Blumenkrantz
7704773619 zink: handle swapchain handoffs around makecurrent
when a new resource is created for an extant swapchain, the existing
acquire (if any) should be transferred to the resource to ensure
expected behavior

this should be enough to fix piglit's glx-make-current

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22431>
2023-04-12 21:43:35 +00:00
Mike Blumenkrantz
5db5218044 zink: track per-image swapchain layouts
this is important for handing off the swapchain between resources
on makecurrent since a context that is made not-current will have its
swapchain resources destroyed while the swapchain persists

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22431>
2023-04-12 21:43:35 +00:00
Bas Nieuwenhuizen
ba73a41a2b radv: Reserve space for fast clear related writes.
Fixes: 9ee67467c9 ("radv: predicate cmask eliminate when using DCC.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22392>
2023-04-12 20:31:47 +00:00
Bas Nieuwenhuizen
1b5bd0f1c0 radv: Reserve space for updating DCC metadata.
Fixes: 9ee67467c9 ("radv: predicate cmask eliminate when using DCC.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22392>
2023-04-12 20:31:47 +00:00