Commit graph

77811 commits

Author SHA1 Message Date
Brian Paul
ee5f5e2269 svga: reduce unmapping/remapping of the default constant buffer
Previously, every time we put shader constants into the default constant
buffer we called u_upload_alloc(), which mapped the buffer, and
u_upload_unmap().  We had to unmap the buffer before calling
svga_buffer_handle() to get the winsys handle for the buffer.  But we
really only need to do that the first time we reference the const buffer.
Now we try to keep the upload manager's buffer mapped until we fill it or
flush the command buffer.

v2: add additional comment on the buffer unmapping code in
svga_context_flush(), per Charmaine.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-09-17 10:09:00 -06:00
Brian Paul
ce3b34b727 svga: optimize memcpy() in svga_buffer_update_hw()
When we migrate a buffer from sw/malloc storage to a hardware buffer,
don't memcpy the whole buffer, just copy the part we've written to.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-09-17 10:08:59 -06:00
Neha Bhende
b7bee25052 svga: Use comparison between svga texture types to use PredCopyRegion command
PredCopyRegion support copy between same type of textures.
Instead of comparing src and dst pipe texture type, compare svga texture
type which can avoid some software fallback.
for example, it avoids a software blit with the Redway3D Aston demo.

Tested piglit tests on VGPU9 and  VGPU10 on GL/DX11Renderer, Redway3D Aston demo

v2: some nit pick suggested by Charmaine.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-09-17 10:08:59 -06:00
Neha Bhende
b9f333cc81 svga: Add function svga_resource_type()
This function returns svga texture type for corresponding pipe texture.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-09-17 10:08:59 -06:00
Samuel Pitoiset
50baaf6bc6 nvc0/ir: fix subops for IMAD
Offset was wrong, it's at bit 8, not 4. Also, uses subr instead
of sub when src2 has neg. Similar to GK110 now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2016-09-17 17:42:45 +02:00
Samuel Pitoiset
9b8b69b3c4 nvc0/ir: fix comments about instructions info
The comment for the commutative flags was wrong because OP_MUL is
before OP_MAD. While we are at it add missing opcodes, and fix
the comment about the short forms.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-17 17:42:40 +02:00
Kenneth Graunke
eaacb27812 mesa: Move buffers-unmapped earlier in check_valid_to_render().
This needs to be above the switch on API, as that can return true
(valid to render) before this error check even had a chance to run.

Fixes ESEXT-CTS.draw_elements_base_vertex_tests.invalid_mapped_bos,
which worked before commit 72f1566f90.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2016-09-16 19:42:56 -07:00
Kenneth Graunke
6b0ba02cae mesa: Expose GL_CONTEXT_FLAGS in ES 3.2.
Fixes four ES32-CTS.context_flags.* tests.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-16 18:55:38 -07:00
Tom Stellard
91ec6e5664 radeonsi/compute: Use the HSA abi for non-TGSI compute shaders v3
This patch switches non-TGSI compute shaders over to using the HSA
ABI described here:

https://github.com/RadeonOpenCompute/ROCm-Docs/blob/master/AMDGPU-ABI.md

The HSA ABI provides a much cleaner interface for compute shaders and allows
us to share more code in the compiler with the HSA stack.

The main changes in this patch are:
  - We now pass the scratch buffer resource into the shader via user sgprs
    rather than using relocations.
  - Grid/Block sizes are now passed to the shader via the dispatch packet
    rather than at the beginning of the kernel arguments.

Typically for HSA, the CP firmware will create the dispatch packet and set
up the user sgprs automatically.  However, in Mesa we let the driver do
this work.  The main reason for this is that I haven't researched how to
get the CP to do all these things, and I'm not sure if it is supported
for all GPUs.

v2:
  - Add comments explaining why we are setting certain bits of the scratch
    resource descriptor.

v3:
  - Use amdgcn-mesa-mesa3d triple instead of amdgcn--mesa3d.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-16 23:07:10 +00:00
Tom Stellard
a2b8346fa6 radeonsi/compute: Add some more debug printfs 2016-09-16 22:51:06 +00:00
Marek Olšák
ae0a4a1299 glsl: remove interpolateAt* instructions for demoted inputs
This fixes 8 fs-interpolateat* piglit crashes on radeonsi, because it can't
handle non-input operands in interpolateAt*.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-16 22:35:08 +02:00
Marek Olšák
d58a3906cb mesa: fix glGetFramebufferAttachmentParameteriv w/ on-demand FRONT_BACK alloc
This fixes 66 CTS tests on st/mesa.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-16 22:35:08 +02:00
Serge Martin
1c8d4c694b clover: fix getting scalar args api size
This fix getting the size of a struct arg. vec3 types still work ok.
Only buit-in args need to have power of two alignment, getTypeAllocSize
reports the correct size in all cases.

Acked-by: Francisco Jerez <currojerez@riseup.net>
2016-09-16 22:09:47 +02:00
Rob Clark
ba8a50955d ttn: fix warning after 7bf76563e
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-09-16 11:55:26 -04:00
Brian Paul
702ff0b9a0 gallium/docs: document alpha_to_coverage and alpha_to_one blend state
The gallium interface defines these like DX10.  Note that OpenGL ignores
these options if MSAA is disabled or the dest buffer doesn't support
MSAA.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-09-16 08:44:26 -06:00
Brian Paul
187c278121 st/mesa: update comment in st_atom_msaa.c
The old comment was a copy and paste mistake.  Indent another comment.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-09-16 08:44:26 -06:00
Brian Paul
a01872f808 st/mesa: only enable MSAA coverage options when we have a MSAA buffer
Regardless of whether GL_MULTISAMPLE is enabled (it's enabled by default)
we should not set the alpha_to_coverage or alpha_to_one flags if the
current drawing buffer does not do MSAA.

This fixes the new piglit gl-1.3-alpha_to_coverage_nop test.

ETQW is a game that enables GL_SAMPLE_ALPHA_TO_COVERAGE without MSAA.
Shrubs along the side of roads were invisible because fragments with
alpha < 0.5 were being discarded (zero coverage).

v2: remove ctx->DrawBuffer != NULL check.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-16 08:44:12 -06:00
Dave Airlie
e1ea36ae71 spirv: use subpass image type (v1.1)
This adds support for the input attachments subpass type
to the SPIRV->NIR pass.

v1.1: drop handling from vtn_handle_texture

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-09-16 15:16:31 +10:00
Dave Airlie
7bf76563e2 glsl: add subpass image type (v2)
SPIR-V/Vulkan have a special image type for input attachments
called the subpass type. It has different characteristics than
other images types.

The main one being it can only be an input image to fragment
shaders and loads from it are relative to the frag coord.

This adds support for it to the GLSL types. Unfortunately
we've run out of space in the sampler dim in types, so we
need to use another bit.

v2: Fixup subpass input name (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-09-16 15:16:31 +10:00
Kenneth Graunke
081f21f29b isl: Finish tiling filtering for Gen6.
Gen6 only has one additional restriction over Gen7+, so we just add it
to the existing gen7 function (which actually covers later gens too).

This should stop FINISHME spew when running GL on Sandybridge.

v2: Fix bytes per block vs. bits per block confusion (Jason) and
    rename function to gen6_filter_tiling (Jason and Chad).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-15 21:21:50 -07:00
Ilia Mirkin
9fec15a7e0 i965: enable ARB_ES3_2_compatibility on gen8+
Note that ASTC support is not actually mandated for this extension to be
exposed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-15 19:29:41 -04:00
Jason Ekstrand
111f6b250d i965/nir: Roll set_default_interpolation into lower_fs_inputs
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-15 13:31:43 -07:00
Jason Ekstrand
246db0063e i965/fs: Use NIR for handling forced per-sample interpolation
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-15 13:31:43 -07:00
Jason Ekstrand
ed65e6ef49 nir: Add a flag to lower_io to force "sample" interpolation
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-15 13:31:43 -07:00
Jason Ekstrand
114874b22b i965/fs: Use sample interpolation for interpolateAtCentroid in persample mode
From the ARB_gpu_shader5 spec:

   The built-in functions interpolateAtCentroid() and interpolateAtSample()
   will sample variables as though they were declared with the "centroid"
   or "sample" qualifiers, respectively.

When running with persample dispatch forced by the API, we interpolate
anything that isn't flat as if it's qualified by "sample".  In order to
keep interpolateAtCentroid() consistent with the "centroid" qualifier, we
need to make interpolateAtCentroid() do sample interpolation instead.
Nothing in the GLSL spec guarantees that the result of
interpolateAtCentroid is uniform across samples in any way, so this is a
perfectly fine thing to do.

Fixes 8 of the new dEQP-VK.pipeline.multisample_interpolation.* Vulkan CTS
tests that specifically validate consistency between the "sample" qualifier
and interpolateAtSample()

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-15 13:31:27 -07:00
Brian Paul
0d2eb8c14d mesa: check for no matrix change in _mesa_LoadMatrixf()
Some apps issue redundant glLoadMatrixf() calls with the same matrix.
Try to avoid setting dirty state in that situation.

This reduces the number of constant buffer updates by about half in
ET Quake Wars.

Tested with Piglit, ETQW, Sauerbraten, Google Earth, etc.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-15 12:00:12 -06:00
Jon Turney
533b3530c1 direct-to-native-GL for GLX clients on Cygwin ("Windows-DRI")
Structurally, this is very similar to the existing Apple-DRI code, except I
have chosen to implement this using the __GLXDRIdisplay, etc. vtables (as
suggested originally in [1]), rather than a maze of ifdefs.  This also means
that LIBGL_ALWAYS_SOFTWARE and LIBGL_ALWAYS_INDIRECT work as expected.

[1] https://lists.freedesktop.org/archives/mesa-dev/2010-May/000756.html

This adds:

* the Windows-DRI extension protocol headers and the windowsdriproto.pc
file, for use in building the Windows-DRI extension for the X server

* a Windows-DRI extension helper client library

* a Windows-specific DRI implementation for GLX clients

The server is queried for Windows-DRI extension support on the screen before
using it (to detect the case where WGL is disabled or can't be activated).

The server is queried for fbconfigID to pixelformatindex mapping, which is
used to augment glx_config.

The server is queried for a native handle for the drawable (which is of a
different type for windows, pixmaps and pbuffers), which is used to augment
__GLXDRIdrawable.

Various GLX extensions are enabled depending on if the equivalent WGL
extension is available.
2016-09-15 13:14:43 +01:00
Kenneth Graunke
3bcdc2e3db mesa: Expose RESET_NOTIFICATION_STRATEGY with KHR_robustness.
This is supposed to be exposed with the GL_KHR_robustness extension,
which we support on ES 2.0 and later.  On desktop GL, it's also exposed
by GL_ARB_robustness, which is supported by all drivers ("dummy_true").
so we also allow desktop GL.

Fixes:
- ES32-CTS.robust.robustness.noResetNotification
- ES32-CTS.robust.robustness.loseContextOnReset

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-15 00:58:47 -07:00
Jason Ekstrand
89a96c8f43 anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW
Without this bit set, the value in "L3 Atomic Disable" won't get applied by
the hardware so we won't properly get L3 atomic caching.

Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex and 198 of
the dEQP-VK.image.atomic_operations.* tests on HSW

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-09-14 17:53:16 -07:00
Jason Ekstrand
a814e18c96 intel/blorp: Stop setting 3DSTATE_DRAWING_RECTANGLE
The Vulkan driver sets 3DSTATE_DRAWING_RECTANGLE once to MAX_INT x MAX_INT
at the GPU initialization time and never sets it again.  The GL driver sets
it every time the framebuffer changes.  Originally, blorp set it to the
size of the drawing area but meant we had to set it back in the Vulkan
driver.  Instead, we can easily just do that in the GL driver's blorp_exec
implementation and not set it in blorp core.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-09-14 17:51:16 -07:00
Jason Ekstrand
b56f509ee0 intel/blorp: Emit 3DSTATE_MULTISAMPLE directly
Previously, we relied on a driver hook for 3DSTATE_MULTISAMPLE.  However,
now that Vulkan and GL use the same sample positions, we can set up
3DSTATE_MULTISAMPLE directly in blorp and delete the driver hook.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-09-14 17:51:16 -07:00
Jason Ekstrand
c779ad3e66 intel: Move Vulkan sample positions to common code
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-09-14 17:51:16 -07:00
Marek Olšák
f019255acf Revert "tgsi/scan: don't set interp flags for inputs only used by INTERP instructions"
This reverts commit 524fd55d2d.

Reason: https://bugs.freedesktop.org/show_bug.cgi?id=97808
2016-09-15 00:47:24 +02:00
Francisco Jerez
6d861968ca i965/vec4: Assert that pull constant load offsets are 16B-aligned.
Non-16B-aligned pull constant loads are unlikely to be particularly
useful given that you can get roughly the same effect by using
swizzles on the result.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:59 -07:00
Francisco Jerez
5ca35c6367 i965/vec4: Assert that ATTR regions are register-aligned.
It might be useful to actually handle this once copy propagation
becomes smarter about register-misaligned offsets.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:59 -07:00
Francisco Jerez
f33a8f8fcf i965/vec4: Don't spill non-GRF-aligned register regions.
A better fix would be to do something along the lines of the FS
back-end spilling code and emit a scratch read before any instruction
that overwrites the register to spill partially due to a non-zero
sub-register offset.  In the meantime mark registers used with a
non-zero sub-register offset as no-spill to prevent the spilling code
from miscompiling the program.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:59 -07:00
Francisco Jerez
8531f943d9 i965/vec4: Fix copy propagation for non-register-aligned regions.
This prevents it from trying to propagate a copy through a
register-misaligned region.  MOV instructions with a misaligned
destination shouldn't be treated as a direct GRF copy, because they
only define the destination GRFs partially.  Also fix the interference
check implemented with is_channel_updated() to consider overlapping
regions with different register offset to interfere, since the
writemask check implemented in the function is only valid under the
assumption that the source and destination regions are aligned
component by component.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:59 -07:00
Francisco Jerez
0e657b7b55 i965/vec4: Compare full register offsets in cmod propagation.
Cmod propagation would misoptimize the program if the destination
offset of the generating instruction wasn't exactly the same as the
source region offset of the copy instruction.  In preparation for
adding support for sub-GRF offsets to the VEC4 IR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:58 -07:00
Francisco Jerez
8bed1adfc1 i965/vec4: Assign correct destination offset to rewritten instruction in register coalesce.
Because the pass already checks that the destination offset of each
'scan_inst' that needs to be rewritten matches 'inst->src[0].offset'
exactly, the final offset of the rewritten instruction is just the
original destination offset of the copy.  This is in preparation for
adding support for sub-GRF offsets to the VEC4 IR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:58 -07:00
Francisco Jerez
3a74e437fd i965/vec4: Don't coalesce registers with overlapping writes not matching the MOV source.
In preparation for adding support for sub-GRF offsets to the VEC4 IR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:58 -07:00
Francisco Jerez
1bb5074474 i965/vec4: Compare full register offsets in opt_register_coalesce nop move check.
In preparation for adding support for sub-GRF offsets to the VEC4 IR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:58 -07:00
Francisco Jerez
3be0d6d040 i965/vec4: Check that the write offsets match when setting dependency controls.
For simplicity just assume that two writes to the same GRF with
different sub-GRF offsets will potentially interfere and break the
dependency control chain.  This is in preparation for adding sub-GRF
offset support to the VEC4 IR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:58 -07:00
Francisco Jerez
b52fefc4d5 i965/vec4: Change opt_vector_float to keep track of the last offset seen in bytes.
This simplifies things slightly and makes the pass more correct in
presence of sub-GRF offsets.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:58 -07:00
Francisco Jerez
230615e228 i965/vec4: Simplify src/dst_reg to brw_reg conversion by using byte_offset().
This should also have the side effect of fixing convert_to_hw_regs()
to handle sub-GRF register offsets.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:58 -07:00
Francisco Jerez
eb746a80e5 i965/ir: Update several stale comments.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:58 -07:00
Francisco Jerez
47784e2346 i965/ir: Don't print ARF subnr values twice.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:58 -07:00
Francisco Jerez
5d65d51e78 i965/vec4: Print src/dst_reg::offset field consistently for all register files.
C.f. 'i965/fs: Print fs_reg::offset field consistently for all
register files.'.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:57 -07:00
Francisco Jerez
ec259f5307 i965/fs: Print fs_reg::offset field consistently for all register files.
The offset printing code in fs_visitor::dump_instruction() was doing
things differently for sources and destinations and for each register
file -- In some cases it would be added to the base register number
fs_reg::nr, in other cases it would follow the base register separated
with a plus sign, in other cases (uniforms) it would do both (!).  The
sub-register offset was also being printed or not rather
inconsistently.  Fix it.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:57 -07:00
Francisco Jerez
950af5ed40 i965/fs: Misc simplification.
Get rid of some leftover redundant arithmetic introduced during the
conversion to byte offsets and sizes that can be simplified easily.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:57 -07:00
Francisco Jerez
80e1d670b4 i965/fs: Get rid of fs_inst::set_smear().
component() was generally a better alternative because of several
issues set_smear() had:

 - It wouldn't take the original stride and offset of the register
   into account, which means that set_smear() on the result of
   e.g. another set_smear() call or an offset() call would give a
   bogus region as result.

 - It was an inherently destructive operation.  See the
   'nir_intrinsic_shader_clock' hunk below for how this could lead to
   subtle bugs in cases where set_smear() was called multiple times on
   the same register like 'r.set_smear(0), r.set_smear(1)' with the
   expectation that each call would return a separate value instead of
   a reference to the same subsequently mutated object.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-09-14 14:50:57 -07:00