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i965/vec4: Don't spill non-GRF-aligned register regions.

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A better fix would be to do something along the lines of the FS
back-end spilling code and emit a scratch read before any instruction
that overwrites the register to spill partially due to a non-zero
sub-register offset.  In the meantime mark registers used with a
non-zero sub-register offset as no-spill to prevent the spilling code
from miscompiling the program.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
This commit is contained in:
Francisco Jerez 2016-09-01 22:36:15 -07:00
parent 8531f943d9
commit f33a8f8fcf
2 changed files with 5 additions and 2 deletions
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5
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
View file

@ -392,7 +392,8 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
*/
if (!can_use_scratch_for_source(inst, i, inst->src[i].nr)) {
spill_costs[inst->src[i].nr] += loop_scale;
if (inst->src[i].reladdr)
if (inst->src[i].reladdr ||
inst->src[i].offset % REG_SIZE != 0)
no_spill[inst->src[i].nr] = true;
}
}
@ -400,7 +401,7 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
if (inst->dst.file == VGRF) {
spill_costs[inst->dst.nr] += loop_scale;
if (inst->dst.reladdr)
if (inst->dst.reladdr || inst->dst.offset % REG_SIZE != 0)
no_spill[inst->dst.nr] = true;
}

2
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -1481,6 +1481,7 @@ vec4_visitor::emit_scratch_read(bblock_t *block, vec4_instruction *inst,
dst_reg temp, src_reg orig_src,
int base_offset)
{
assert(orig_src.offset % REG_SIZE == 0);
int reg_offset = base_offset + orig_src.offset / REG_SIZE;
src_reg index = get_scratch_offset(block, inst, orig_src.reladdr,
reg_offset);
@ -1498,6 +1499,7 @@ void
vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst,
int base_offset)
{
assert(inst->dst.offset % REG_SIZE == 0);
int reg_offset = base_offset + inst->dst.offset / REG_SIZE;
src_reg index = get_scratch_offset(block, inst, inst->dst.reladdr,
reg_offset);