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Author SHA1 Message Date
Tatsuyuki Ishi
eb0419a1aa radv: Remove aspect mask "expansion" for copy_image. 
The Vulkan spec says multi-planar images can only be copied on a
per-plane basis. The COLOR_BIT to "all planes" expansion applies to
image memory barriers which is completely unrelated.

Remove the expansion logic to simplify the code. Add assertions to
clearly describe the invariant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26364>
 2023-12-01 01:52:04 +00:00
Marek Olšák
7ffb65f935 ac: add an IB parser that gathers context rolls 
This is an important performance bottleneck analysis tool.

Try it with radeonsi: AMD_ROLLS=filename app

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
 2023-12-01 01:15:55 +00:00
Marek Olšák
f0cb8852a4 ac: move the IB parsers into ac_parse_ib.c 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
 2023-12-01 01:15:55 +00:00
Marek Olšák
c5fe2780e6 ac: rename ac_parse_ib.c -> ac_ib_parser.c 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
 2023-12-01 01:15:55 +00:00
Peyton Lee
3ec397819e amd: add new hardware ip for vpe 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Peyton Lee
17c20ceda7 amd,radeonsi: add libvpe 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Signed-off-by: Alan Liu <haoping.liu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Lynne
aff59c63eb radv: change queue family order in radv_get_physical_device_queue_family_properties 
Fixes: 748b7f80ef ("radv: Move sparse binding into a dedicated queue.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26428>
 2023-11-30 22:45:49 +00:00
Rhys Perry
5bc27e80c9 ac/nir: fix 32-bit offset global access optimization 
Since 38cff03e58 ("radv: use nir_lower_conv64"), u2u64(a) is replaced
with pack_64_2x32_split(a, 0).

fossil-db (navi31):
Totals from 1203 (1.52% of 79330) affected shaders:
MaxWaves: 33685 -> 33813 (+0.38%)
Instrs: 1407031 -> 1374689 (-2.30%); split: -2.32%, +0.02%
CodeSize: 7088652 -> 6917320 (-2.42%); split: -2.43%, +0.01%
VGPRs: 69276 -> 68988 (-0.42%); split: -0.43%, +0.02%
SpillSGPRs: 982 -> 977 (-0.51%); split: -0.92%, +0.41%
Latency: 12536511 -> 12451605 (-0.68%); split: -0.94%, +0.27%
InvThroughput: 2456803 -> 2431241 (-1.04%); split: -1.09%, +0.05%
VClause: 27624 -> 27832 (+0.75%); split: -1.88%, +2.64%
SClause: 31757 -> 32702 (+2.98%); split: -0.53%, +3.51%
Copies: 90923 -> 91238 (+0.35%); split: -1.47%, +1.81%
Branches: 25127 -> 25128 (+0.00%); split: -0.00%, +0.01%
PreSGPRs: 46025 -> 46068 (+0.09%); split: -0.53%, +0.62%
PreVGPRs: 53944 -> 53488 (-0.85%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
 2023-11-30 21:50:21 +00:00
Rhys Perry
10ba06960f ac/nir: ignore 8/16-bit global access offset 
This was found by inspection, I'm not sure it can even happen.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
 2023-11-30 21:50:21 +00:00
Boyuan Zhang
d07517d19f radeonsi: add new interface to handle multi slice reflist 
Add new flag and buffer to handle multi slice reflist case for hevc.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26081>
 2023-11-30 08:39:31 -05:00
Bas Nieuwenhuizen
748b7f80ef radv: Move sparse binding into a dedicated queue. 
1) This better reflects the reality that we only have one timeline
   of sparse binding changes.

2) Allows making it a threaded queue from the start in prep of
   explicit sync stuff.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
 2023-11-29 17:37:37 +00:00
Bas Nieuwenhuizen
00faefa08e radv: Remove the sparse binding queue from coherent images. 
Never access the image on the queue family, so no need.

(Technically not sure if this is needed for Vulkan, somewhat of
 a backstop in case apps do it)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
 2023-11-29 17:37:37 +00:00
Bas Nieuwenhuizen
6ff98f9313 radv: Add implementation of cmd buffers for a sparse binding queue. 
None of the commands are allowed on these ...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
 2023-11-29 17:37:37 +00:00
Alyssa Rosenzweig
d50d9eccad ac,radv,radeonsi: use common 1D texture lowering 
It was pulled from ac.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26397>
 2023-11-29 14:04:15 +00:00
Konstantin Seurer
11897376c7 radv/rt: Skip null checks for small case counts 
The individual cases make sure the sbt_idx is not null implicitly
because the handles are always != 0.

Totals from 60 (22.56% of 266) affected shaders:
Instrs: 47841 -> 47655 (-0.39%)
CodeSize: 255028 -> 253460 (-0.61%)
Latency: 1179658 -> 1225311 (+3.87%); split: -0.02%, +3.89%
InvThroughput: 224122 -> 232851 (+3.89%); split: -0.02%, +3.92%
Copies: 12049 -> 12043 (-0.05%); split: -0.37%, +0.32%
Branches: 3312 -> 3290 (-0.66%)
PreSGPRs: 3494 -> 3472 (-0.63%)

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25089>
 2023-11-28 22:58:35 +00:00
Konstantin Seurer
fe674f67b1 radv/rt: Use a helper for inlining non-recursive stages 
So we don't have to write the same logic multiple times.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25089>
 2023-11-28 22:58:35 +00:00
Samuel Pitoiset
02ef01fa95 radv: enable DGC preprocessing for IBO 
This seems to improve performance for Starfield by +1% and Halo Infinite
by +15%!

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10025
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Samuel Pitoiset
e59a16bbb8 radv: use an indirect draw when IBO isn't updated as part of DGC 
To remove the dependency on the cmd buffer state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Samuel Pitoiset
2807e27231 radv: set the stream VA for DGC graphics 
This will be used to emit indirect draws when needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Samuel Pitoiset
88bbdfd23e radv: remove useless NIR instructions when emitting IBO with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Georg Lehmann
4b9618ceec aco: add test for post-ra DPP clobbered in linear cfg 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26373>
 2023-11-28 12:48:56 +00:00
Georg Lehmann
576afa8540 aco: don't optimize DPP across more than one block 
Register write tracking doesn't work for inactive lanes, so this was unsafe.

Foz-DB Navi31:
Totals from 8 (0.01% of 78196) affected shaders:
Instrs: 11513 -> 11515 (+0.02%)
CodeSize: 61056 -> 61064 (+0.01%)

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10197
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26373>
 2023-11-28 12:48:56 +00:00
Samuel Pitoiset
06c9e69f44 radv/ci: add new flakes for VEGA10 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26384>
 2023-11-28 09:04:08 +01:00
Rhys Perry
2d98236dd5 ac/nir: fix partial mesh shader output writes on GFX11 
Fixes dEQP-VK.mesh_shader.ext.smoke.monolithic.mesh_shader_triangle with
nir_opt_combine_stores disabled.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 240e16fc8e ("ac/nir/ngg: Use attribute ring for mesh shader params.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25530>
 2023-11-27 20:11:03 +00:00
Marek Olšák
3a0a3a5c35 radeonsi: implement gl_Layer in FS as a system value 
This replaces the vec4 FS input with the Ancillary VGPR input.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26274>
 2023-11-24 15:37:24 +00:00
Marek Olšák
e0a24c7fe0 ac/nir: add kill_layer flag to VS/GS/NGG lowering 
When the framebuffer state has only 1 layer, the output has no effect.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26274>
 2023-11-24 15:37:24 +00:00
Kai Wasserbäch
bc7e363f8e fix: ac/llvm: LLVM 18: remove useless passes, partially removed upstream 
Upstream removed llvm::createLoopSinkPass() in commit
<b9975cec0e>
and there is no useful alternative except moving to the new pass
manager.

On top of that, the usage of this optimisation pass and
PromoteMemoryToRegisterPass were just useless, according to the
upstream developer of the commit named above. Therefore the easiest
solution is, as him, Marek and Dave suggested, to just remove these two
passes from the pipeline for now.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10192
Reference: https://github.com/llvm/llvm-project/pull/72811
Reference: b9975cec0e
Suggested-by: Dave Airlie <airlied@redhat.com>
Suggested-by: Aiden Grossman <agrossman154@yahoo.com>
Suggested-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26336>
 2023-11-24 14:11:09 +00:00
Samuel Pitoiset
ad7efdea6e radv: do not set OREO_MODE to fix rare corruption on GFX11 
Ported from RadeonSI 3f108e7615.
Seems to be a recommendation from the AMD hw team.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26333>
 2023-11-23 17:22:04 +00:00
Samuel Pitoiset
46cc7ffb79 radv: add missing FDCC_CONTROL bits for GFX1103 R2 
Ported from RadeonSI.
Found by inspection, untested.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26318>
 2023-11-23 13:56:53 +00:00
Samuel Pitoiset
ab34603115 radv: disable TC-compatible HTILE on Tonga and Iceland 
According to RadeonSI, TC-compat HTILE have issues on Tonga/Iceland
(first GFX8 chips) and a bunch of games seem to have issues.

Let's disable it instead of using a feature that is known broken.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7101
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3894
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26204>
 2023-11-23 12:55:47 +00:00
Daniel Schürmann
3b10547e67 aco: enable helper lanes if shader->info.fs.require_full_quads 
This enables helper invocations also for lowered quad group operations.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26026>
 2023-11-22 11:32:53 +01:00
Samuel Pitoiset
f39ed0063b radv/ci: add missing expected failures for mesh queries on VANGOGH 
Forgot to add them.

Fixes: b975d4e800 ("radv: enable meshShaderQueries on GFX10.3")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26331>
 2023-11-22 08:35:54 +01:00
Georg Lehmann
0a5d3ac8d2 aco/sched: treat p_dual_src_export_gfx11 like export 
This prevents the scheduler from moving the dual source export above mrtz
export, which caused hangs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10173

Cc: mesa-stable
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26317>
 2023-11-21 18:11:45 +00:00
Samuel Pitoiset
b975d4e800 radv: enable meshShaderQueries on GFX10.3 
GFX11 support will come later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset
6c7265338d radv: add support for task shader invocations queries on GFX10.3 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset
623b7033c5 radv: make some gang functions non-static 
They will be used to create a gang CS when beginning a query if not
already present.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset
1b3efecd56 radv: rework gfx10_copy_gds_query() slightly 
To prepare for the same function with ACE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset
b7d668a819 radv: add support for mesh shader invocations queries on GFX10.3 
Also emulated with a GDS atomic counter in shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset
48aabaf225 radv: do not harcode the pipeline stats mask for query resolves 
Otherwise, mesh/task shader invocations would be ignored.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset
272ad65397 radv: bump the pipeline state query size to 14 on GFX10.3 
GFX10.3 doesn't natively support mesh/task shader invocations query
and they need to be emulated in shaders. In order to share more code
between GFX10.3 and GFX11, it's easier to use the same size as GFX11.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset
7b13500a99 radv: define new pipeline statistics indices for mesh/task on GFX11 
GFX11 uses pipeline statistics for mesh/task queries but on GFX10.3
they need to be emulated. Though the number of mesh/task shader
invocations would be copied to the pipeline statistics range to
simplify the implementation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset
2b93e9a02b radv: add support for mesh primitives queries on GFX10.3 
This query is emulated using a GDS atomic counter in shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:48 +00:00
Samuel Pitoiset
bc6d29b0ca radv: add radv_physical_device::emulate_mesh_shader_queries for GFX10.3 
GFX11 supports them natively but not GFX10.3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:48 +00:00
Samuel Pitoiset
7d1cc5ec3d radv: rename ps_epilog_inputs to colors for PS epilogs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26231>
 2023-11-21 08:47:50 +00:00
Samuel Pitoiset
e1345c5295 aco: rename color_exports to exports in create_fs_jump_to_epilog() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26231>
 2023-11-21 08:47:50 +00:00
Chia-I Wu
16a270f646 radv: disable TC-compat htile on GFX9 in some cases 
Similar to commit a38de4c011 ("radv: disable tc_compatible_cmask on
GFX9 in some cases"), GFX9 seems to have issues with TC-compat htile as
well.

I've only seen this with D16 and sample count 4.  But I am not sure
about the exact condition.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10161
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26263>
 2023-11-20 20:09:44 +00:00
Eric Engestrom
46c9128117 amd/ci: track changes to the traces config file as well 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26278>
 2023-11-20 15:23:40 +00:00
Eric Engestrom
4de3ce1f2c ci/piglit: specify only the traces file in the job config 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26278>
 2023-11-20 15:23:40 +00:00
Samuel Pitoiset
fc044928b2 radv: re-enable sparseResidencyImage3D on POLARIS10+ 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7214
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26260>
 2023-11-20 08:30:05 +01:00
Samuel Pitoiset
e02a1f0a44 ac/surface: change tile mode for 3D PRT surfaces with bpp < 64 on GFX6-8 
This is loosely based on PAL. This seems to fix 3D PRT support with
RADV on Polaris10. THIN means the tile is a 2D slice. THICK means the
tile is a 3D box.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26260>
 2023-11-20 08:29:19 +01:00