Commit graph

62137 commits

Author SHA1 Message Date
Jason Ekstrand
e956f6ad30 intel/isl: Allow Ys tiling
Ys & Yf are both implemented in ISL now, we still have some Yf issues
to investigate. Instead of disabling them in ISL, we disable them in
the two drivers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Karol Herbst
5263802618 rusticl/memory: do not verify pitch for IMAGE1D_BUFFER
Devices might report an image_pitch_alignment of 0 leading to a division
by 0 trap.

Fixes: 06daa03c5c ("rusticl: Implement spec for cl_khr_image2d_from_buffer")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24993>
2023-09-01 20:06:30 +00:00
Eric Engestrom
a8c7a2fb69 ci/amd: split the polaris10 rules into one for each farm
There is now one polaris10 in each farm, so we need two rules for which
one to use.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24996>
2023-09-01 19:35:33 +00:00
Karol Herbst
46c17a8e54 rusticl/queue: properly implement clCreateCommandQueueWithProperties
It didn't do any of the error checking, but it was supposed to be. Also
the error checking was slightly wrong and we should return
CL_INVALID_QUEUE_PROPERTIES instead of CL_INVALID_VALUE for unsupported
properties.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24991>
2023-09-01 13:51:22 +00:00
Samuel Pitoiset
969f7b97fd zink/ci: add zink-radv-polaris10-valve
This introduces Zink/RADV testing on Polaris10!

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24976>
2023-09-01 12:52:42 +00:00
Qiang Yu
1f3858509c radeonsi: enable aco compile for part mode standalone vs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
287f7a9c35 radeonsi: set vs has prolog aco shader info
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
4247b742ec radeonsi: add vs prolog aco build
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
8c3b5ce0c4 radeonsi: fix aco options has_ls_vgpr_init_bug setup
Fixes: b313d950e2 ("radeonsi: enable aco compile for mono merged LS/HS")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
ec57236824 radeonsi: extract si_get_vs_prolog_args to be shared with aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
07b62af810 radeonsi: remove is_monolithic from vs prolog key
We do not generate vs prolog for monolithic shader any more.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
4c10bf1e6d radeonsi: fill aco_shader_info->is_monolithic
Fixes: 80177e0296 ("aco: add support for compiling VS+TCS separately on GFX9+")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24944>
2023-09-01 03:06:03 +00:00
Karol Herbst
667375999c rusticl/event: disable profiling for devices without timestamps
Timestamp queries are strictly required, but a bit odd to not expose CL
for not supporting it...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24938>
2023-09-01 02:48:55 +00:00
Karol Herbst
8e4d51aa1f rusticl/query: fix use-after-free, but also fix incorrect usage of unsafe
`PipeQuery::new` create a `PipeQuery` wrapper before handling errors, so
we ended up calling `drop` and destroy_query, meaning the latter ended up
being called twice.

While at it, also restrict visibility of related methods and add some
unsafe declarations.

Fixes: 52e53938c3 ("rusticl: Wrap pipe queries")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24938>
2023-09-01 02:48:55 +00:00
Lang Yu
f2c8cb2649 radeonsi: use wave size to determine index stride
Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>
2023-08-31 20:30:03 +00:00
Lang Yu
42abb231aa radeonsi: use AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 to determine wave size
Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>
2023-08-31 20:30:03 +00:00
Karol Herbst
1a20ac7891 rusticl/disk_cache: fix stack corruption
The length passed to mesa_bytes_to_hex is the one of the input, not output
data.

Fixes: fbe9a7ca3e ("rusticl/mesa: create proper build-id hash for the disk cache")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24967>
2023-08-31 15:17:50 +00:00
Lionel Landwerlin
bcc0ec8e6c anv: enable KHR_maintenance5
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24387>
2023-08-31 16:02:52 +03:00
Konstantin Seurer
8bc0f6be67 lavapipe: Fix the locking around cso destruction
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24956>
2023-08-31 07:54:44 +00:00
Konstantin Seurer
3d0ed8bb26 lavapipe: Avoid lowering shaders twice
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9726
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24956>
2023-08-31 07:54:44 +00:00
Dave Airlie
55e348b879 llvmpipe/fs: rewrite output finding using nir.
Reviewed-by: Brian Paul	<brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24817>
2023-08-31 07:13:33 +00:00
Dave Airlie
89451e79cd llvmpipe/fs: drop the simple shader logic
It's been turned off since 2013.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24817>
2023-08-31 07:13:33 +00:00
Dave Airlie
a63c2daf7a llvmpipe/fs: start using nir info in some places.
Reviewed-by: Brian Paul	<brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24817>
2023-08-31 07:13:33 +00:00
Dave Airlie
f36488a406 llvmpipe/analyse: drop TGSI path.
This drop the AERO path, this should probably be reworked using NIR.

Reviewed-by: Brian Paul	<brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24817>
2023-08-31 07:13:33 +00:00
Dave Airlie
d2c4b8b32a llvmpipe/fs: switch to using tgsi->nir instead of handling tgsi
This just swaps, lots of cleanup after this.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24817>
2023-08-31 07:13:33 +00:00
Alyssa Rosenzweig
f80c57c38f treewide: Use nir_before/after_impl for more elaborate cases
Via Coccinelle patch:

    @@
    expression func_impl;
    @@

    -nir_before_block(nir_start_block(func_impl))
    +nir_before_impl(func_impl)

    @@
    expression func_impl;
    @@

    -nir_after_block(nir_impl_last_block(func_impl))
    +nir_after_impl(func_impl)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24910>
2023-08-30 19:30:58 +00:00
Alyssa Rosenzweig
25cc04c59b treewide: Use nir_before/after_impl in easy cases
These open-code the same idiom as the helper.

Via Coccinelle patch:

    @@
    expression func_impl;
    @@

    -nir_before_cf_list(&func_impl->body)
    +nir_before_impl(func_impl)

    @@
    expression func_impl;
    @@

    -nir_after_cf_list(&func_impl->body)
    +nir_after_impl(func_impl)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24910>
2023-08-30 19:30:58 +00:00
Karol Herbst
7d29a264ea rusticl: reduce global_invocation_id_zero_base to 32 bit
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24939>
2023-08-30 16:25:40 +00:00
Mike Blumenkrantz
ae5e2c1fea zink: add lavapipe flake
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24951>
2023-08-30 14:50:05 +00:00
Corentin Noël
9c39ea796c virgl: Do not expose EXT_texture_mirror_clamp when using a GLES host
The GL_MIRROR_CLAMP_EXT wrap parameter is never available in GLES.

This fixes the `spec@!opengl 1.1@texwrap 2d proj` piglit test when using a GLES
host.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24935>
2023-08-30 12:57:58 +00:00
Karol Herbst
bf4243f080 gallivm/nir: drop 64 bit handling for cl workgroup intrinsics
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>
2023-08-30 07:04:33 +00:00
Karol Herbst
1b22b67199 nir: make workgroup_id 32 bit only
No backend supports 64 bit values natively anyway.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>
2023-08-30 07:04:33 +00:00
Iago Toral Quiroga
ade44ad82e v3d,v3dv: use fquantize2f16 lowering in NIR
Ths is equivalent to what we have been doing in the backend.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24924>
2023-08-30 06:26:35 +00:00
Lionel Landwerlin
45e2efbe85 zink+anv: add regression testing with pipeline libraries
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24716>
2023-08-29 23:19:13 +00:00
Lionel Landwerlin
9bf2a89127 intel/compiler: fix dynamic alpha-to-coverage handling
Got the wrong logic operation. Let's reuse the nicer NIR builder
helper.

Fixes a bunch of KHR-GL46.sample_variables.mask.rgba8.*.samples*.mask*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: fd7debc8bb ("intel/fs: make alpha_to_coverage a tristate")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9568
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24716>
2023-08-29 23:19:12 +00:00
Ian Romanick
927a24db14 intel/fs: New VGRF packing scheme for constant combining
Each block is processed separately.  VGRF channels that are allocated to
values that are only used in a particular block are made available in
other blocks.

This is almost always an improvement, but there are some pessimal cases
where it goes horribly wrong.  Imagine a shader with two blocks.  In
that shader, the first block has 5 constants used in the first block and
the second block.  Three other constants are only used in the first
block.  The second block has 15 constants that are used only in the
block.  The static VGRF usage is 3 regardless of packing.  However,
scheduling may be able to shorten the live range of the first VGRF when
it only has values that came from the first block (because three of the
values are dead on entry to the second block).

This used to occurs in a Mad Max shader on Broadwell.  That shader
went from 0:0 spills:fills to 107:52.  Some changes over the last
year, I'm assuming !13734, have prevented this case from occuring.

This change created a lot of churn on Haswell and Ivy Bridge.  This
seems to be primarily due to all the extra constants used for coissue,
but I did not investigate very deeply.  On older platforms, there were
no changes to spills or fills.  As a result, this is only used on
Broadwell and newer platforms.

v2: Update expected checksum for pixmark-piano-v2.trace on
gl-zink-anv-tgl. See #9714 for more details.

shader-db results:

Tiger Lake
total instructions in shared programs: 21101332 -> 21102084 (<.01%)
instructions in affected programs: 863686 -> 864438 (0.09%)
helped: 463 / HURT: 437

total cycles in shared programs: 790573225 -> 790664391 (0.01%)
cycles in affected programs: 92546803 -> 92637969 (0.10%)
helped: 558 / HURT: 629

total spills in shared programs: 3959 -> 3951 (-0.20%)
spills in affected programs: 184 -> 176 (-4.35%)
helped: 2 / HURT: 0

total fills in shared programs: 2639 -> 2631 (-0.30%)
fills in affected programs: 184 -> 176 (-4.35%)
helped: 2 / HURT: 0

LOST:   1
GAINED: 5

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 19945216 -> 19944711 (<.01%)
instructions in affected programs: 139569 -> 139064 (-0.36%)
helped: 66 / HURT: 3

total cycles in shared programs: 858410082 -> 857381323 (-0.12%)
cycles in affected programs: 383825958 -> 382797199 (-0.27%)
helped: 1012 / HURT: 1055

total spills in shared programs: 6190 -> 6116 (-1.20%)
spills in affected programs: 891 -> 817 (-8.31%)
helped: 66 / HURT: 3

total fills in shared programs: 7382 -> 7238 (-1.95%)
fills in affected programs: 1538 -> 1394 (-9.36%)
helped: 66 / HURT: 3

LOST:   5
GAINED: 8

Broadwell
total instructions in shared programs: 17820886 -> 17812515 (-0.05%)
instructions in affected programs: 800512 -> 792141 (-1.05%)
helped: 385 / HURT: 1

total cycles in shared programs: 904482935 -> 903102070 (-0.15%)
cycles in affected programs: 422427015 -> 421046150 (-0.33%)
helped: 1091 / HURT: 812

total spills in shared programs: 17908 -> 16576 (-7.44%)
spills in affected programs: 9459 -> 8127 (-14.08%)
helped: 386 / HURT: 0

total fills in shared programs: 25397 -> 22354 (-11.98%)
fills in affected programs: 15504 -> 12461 (-19.63%)
helped: 385 / HURT: 1

LOST:   2
GAINED: 2

No shader-db changes on Haswell or older platforms.

fossil-db results:

Tiger Lake
Instructions in all programs: 156881463 -> 156890970 (+0.0%)
Instructions helped: 9033
Instructions hurt: 10285

Cycles in all programs: 7532597466 -> 7529647924 (-0.0%)
Cycles helped: 10548
Cycles hurt: 13667

Spills in all programs: 5490 -> 5110 (-6.9%)
Spills helped: 100
Spills hurt: 3

Fills in all programs: 6123 -> 5752 (-6.1%)
Fills helped: 100
Fills hurt: 3

Gained: 17
Lost: 47

Ice Lake
Instructions in all programs: 141309644 -> 141309603 (-0.0%)
Instructions helped: 9
Instructions hurt: 4

Cycles in all programs: 9095812690 -> 9097008049 (+0.0%)
Cycles helped: 14288
Cycles hurt: 16381

Spills in all programs: 7418 -> 7404 (-0.2%)
Spills helped: 9
Spills hurt: 4

Fills in all programs: 8326 -> 8321 (-0.1%)
Fills helped: 9
Fills hurt: 4

Skylake
Instructions in all programs: 131872347 -> 131870690 (-0.0%)
Instructions helped: 111
Instructions hurt: 3

Cycles in all programs: 8800835649 -> 8802483884 (+0.0%)
Cycles helped: 9415
Cycles hurt: 9678

Spills in all programs: 6917 -> 6476 (-6.4%)
Spills helped: 111
Spills hurt: 3

Fills in all programs: 7584 -> 7354 (-3.0%)
Fills helped: 111
Fills hurt: 3

Lost: 5

Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7698>
2023-08-29 19:01:37 +00:00
David Rosca
32610bee4c gallium/auxiliary/vl: Set vertex element src_stride in vl_deint_filter
Fixes: 7672545223 ("gallium: move vertex stride to CSO")

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24926>
2023-08-29 12:21:06 +00:00
David Heidelberg
ba5085469d ci/virgl: flakes in functional.draw_buffers_indexed group
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24922>
2023-08-29 11:11:51 +00:00
Mike Blumenkrantz
f7f6a015d0 zink: remove sync TODO
after investigating, this is pointless and won't ever generate any value

fixes #9016

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>
2023-08-29 04:30:46 +00:00
Mike Blumenkrantz
361f7796b4 zink: simplify some image barrier conditionals
no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>
2023-08-29 04:30:46 +00:00
Mike Blumenkrantz
4d0e975a81 zink: make image barrier init functions void return
the return value was never used

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>
2023-08-29 04:30:46 +00:00
Mike Blumenkrantz
43be9a867e zink: reset unordered flags for image barriers on non-matching batch access
this allows more reordering when the first barrier in a new cmdbuf can
be reordered after previous ordered access exists

KHR-GLES3.copy_tex_image_conversions.required.texture2d_cubemap_negz:
before - ordered 68
after - ordered 16

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>
2023-08-29 04:30:46 +00:00
Mike Blumenkrantz
e64a47cee7 zink: force-reset unordered flags for buffer barriers on non-matching batch access
this should allow slightly better reordering

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>
2023-08-29 04:30:46 +00:00
Mike Blumenkrantz
6776f7c6d3 zink: fix optimal_keys warning message
needs more newlines

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24894>
2023-08-29 01:12:48 +00:00
Mike Blumenkrantz
b8ea9724fa zink: be consistent with ds3 state resetting for blits
handle no-stipple case

Fixes: 122ffb0c88 ("zink: unset line stipple ds3 state flags when stipple not available")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24894>
2023-08-29 01:12:48 +00:00
Mike Blumenkrantz
87044cfe33 zink: break out ds3 state resetting
no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24894>
2023-08-29 01:12:48 +00:00
Ruijing Dong
b39d328dcb frontends/va: checking va version for av1enc support
need to ensure va version >= 1.16 to support av1enc.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24901>
2023-08-28 22:32:42 +00:00
Sil Vilerino
7c98510d17 d3d12: Fix H264 interlaced decode
Have to set the interlaced field of the surface before
end_frame is called in the pipe codec object so the info
is available to the frontend/va, instead of setting it
directly in end_frame like before.

Fixes: 578e10e157 ("frontends/va: Alloc interlaced surface for interlaced pics")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24909>
2023-08-28 13:15:55 -04:00
Sil Vilerino
c3cf7f3e35 d3d12: Fix Map/Unmap of YUV resources
Restore transfer box original size after temporal per plane
dimension calculation.

Currently the returned transfer object on Map will have the
size (usually downsampled) of the latest plane instead of
the overall resource size. Then on unmap, when flushing the
changes the received transfer box has the wrong dimensions
and only partial data is flushed.

Fixes: 12a4f2c132 ("frontends/va: Also map VAImageBufferType for reading")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24909>
2023-08-28 13:15:55 -04:00
Vinson Lee
f816578e4e nv50: Remove unused value
Fix defect reported by Coverity Scan.

Unused value (UNUSED_VALUE)
assigned_pointer: Assigning value from &nv50->vtxbuf[b] to vb here, but
that stored value is overwritten before it can be used.

Fixes: 7672545223 ("gallium: move vertex stride to CSO")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24801>
2023-08-26 12:17:21 -07:00