Commit graph

174628 commits

Author SHA1 Message Date
Alyssa Rosenzweig
e890bb0e75 asahi: Don't depend on glibc to decode
fopencookie is a glibc feature, so we can't use it on macOS (and
probably other libc's?). It's only used for the hypervisor interface,
though, so we can just make the hypervisor piece glibc-only while
otherwise fixing the wrap.dylib build.

Fixes: ee83453f69 ("asahi: Add a shared library interface for decode")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24293>
2023-07-22 12:42:58 -04:00
Eric Engestrom
f997d32f9f asahi: drop unused include paths
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24287>
2023-07-22 10:10:03 +00:00
Christian Gmeiner
2572a96162 ci/etnaviv: update ci expectations
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24291>
2023-07-22 04:16:32 +00:00
Chia-I Wu
5cca1124d1 amd/ci: update radv-stoney-aco-fails.txt for depth/stencil resolve
image_2d_16_64_6 ones have been fixed by the previous commit.  The
others are outdated.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23959>
2023-07-22 02:32:31 +00:00
Chia-I Wu
e7c4ebc0cd radv: disable tc-compat htile for layered images on gfx8
sliceInterleaved may be true for layered images on gfx8.  Such a htile
cannot be cleared with radv_clear_htile.

Fixes 24 failures in
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.* on GFX8.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23959>
2023-07-22 02:32:31 +00:00
Thomas H.P. Andersen
d84d5ff0ce tgsi: drop two unused functions
Removes:
* tgsi_util_get_src_from_ind
* tgsi_full_src_register_from_dst

The last usage of these got removed in !24175

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24283>
2023-07-22 02:04:57 +00:00
Yiwei Zhang
2ed4f04869 venus: use in_render_pass to skip present_src counting
It's an early return also benefiting dynamic rendering. We then no
longer need to track the legacy pass from inheritance info.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:43 +00:00
Yiwei Zhang
e47da97be6 venus: refactor more cmd states into cmd builder
This change:
- adds helpers for cmd begin/end rendering
- simplifies cmd reset
- updates ordering to align with cmd builder

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:43 +00:00
Yiwei Zhang
10c791619c venus: avoid redundant tracking of render pass
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:43 +00:00
Yiwei Zhang
540242f9ff venus: add helpers to track subpass view mask
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:43 +00:00
Yiwei Zhang
311a0eeb21 venus: cleanup vn_cmd_begin_render_pass usage
For secondary command buffers, vn_cmd_begin_render_pass was only used to
track inherited render pass previously. So we clean it up.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:43 +00:00
Yiwei Zhang
81b69f8e8b venus: use tracked queue_family_index from the cmd pool
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:43 +00:00
Yiwei Zhang
72728f83ed venus: remove redundant fb tracking from cmd builder
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:43 +00:00
Yiwei Zhang
f0b5a6335d venus: move transient storage from cmd to pool
The storage is for command scope usage, so it fits better for the pool.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:43 +00:00
Yiwei Zhang
566df7821b venus: log and doc the broken query feedback in suspended render pass
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:43 +00:00
Yiwei Zhang
d13bf8f6b1 venus: fix cmd state leak across implicit reset
Reset cmd states during vkBeginCommandBuffer regardless of the
VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT for simplicity.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:42 +00:00
Yiwei Zhang
a9f058d614 venus: fix a cmd builder render_pass state leak across reset
Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>
2023-07-22 01:49:42 +00:00
Dave Airlie
2b03938f27 gallivm: fix atomic global temporary storage.
Fixes regression on llvm15 with
piglit tests/cl/program/execute/builtin/atomic/atomic_xchg-global.cl

Fixes: f281290005 ("gallivm: Fix atomic_global types")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24267>
2023-07-21 20:48:16 +00:00
Charmaine Lee
9c17d9df43 svga: set clear_texture to NULL for vgpu9
With PIPE_CAP_CLEAR_TEXTURE removed, we need to set clear_texture to NULL
on svga vgpu9 device so it can use the fallback path.

Fixes: a1eabeff66 ("gallium: remove PIPE_CAP_CLEAR_TEXTURE")

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24264>
2023-07-21 17:36:31 +00:00
Yiwei Zhang
fd9a0ecc86 ci/venus: update venus-lavapipe expectations
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24263>
2023-07-21 17:11:26 +00:00
Yiwei Zhang
8cb7bab341 lvp: avoid reading immutable sampler from desc write info
Lavapipe has switched to layer push descriptor support atop descriptor
updates internally since 12a7fc51c7, so
it must skip retrieving immutable samplers from the write info even if
the update call itself is blessed by the spec to not hit that case.

Fixes: 12a7fc51c7 ("lavapipe: Rework descriptor handling")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24263>
2023-07-21 17:11:26 +00:00
Lionel Landwerlin
1f3e320d15 vulkan: bump header register to 1.3.258
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24279>
2023-07-21 16:36:26 +00:00
Connor Abbott
c75bf084d0 tu, freedreno/a6xx: Remove has_ccu_flush_bug
Based on the previous commit, this isn't actually a bug and is expected
behavior. Turnip should already be handling it correctly for user
flushes, we just have to make sure to handle it for flushes we insert
ourselves in turnip and freedreno.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24162>
2023-07-21 16:02:50 +00:00
Connor Abbott
847834461e tu: Fix and simplify execution dependency handling
When I wrote this code, I was under the impression that at most one
context from each cluster could be executing at a time. This would mean
that we could treat clusters as pipeline stages and only insert a WFI if
there was a bubble where an earlier stage depends on the result of a
later stage.

This mental model was wrong, though. Experiments on a6xx show it's
possible for two contexts to be executing simultaneously, even though
there are only two contexts - register writing is just stalled until the
earliest-launched context finishes.

This means that the mental model is now much simpler. Any draw can, in
theory, execute in parallel with any previous draw, blit, flush, etc,
although it seems that flushes do wait for any earlier work to finish.
Clusters are mostly just an implementation detail that only matter in
some corner cases, like setting a non-context register (written in the
last cluster) that is used by an earlier cluster that can race ahead of
the write.

An example where this makes a difference is a fragment shader that
writes an image via stib followed by a blit from that same image.
Because both operations happen in the same cluster and use the same
cache, we wouldn't emit anything in the barrier, however actually we
still need to WFI.

This was getting worse on a7xx because later clusters now have 4
contexts, making it easier for draws to be executed in parallel. However
AFAICT it was already a problem on a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24162>
2023-07-21 16:02:50 +00:00
Connor Abbott
ed02094235 tu: Fix vk2tu_*_stage flag type
New flags were silently getting dropped.

Fixes: 59259a0167 ("tu: Convert to sync2 entrypoints")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24162>
2023-07-21 16:02:50 +00:00
Eric Engestrom
e1abf85bf5 docs: update calendar for 23.1.4
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24281>
2023-07-21 15:53:50 +00:00
Eric Engestrom
0720b0a613 docs: add sha256sum for 23.1.4
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24281>
2023-07-21 15:53:50 +00:00
Eric Engestrom
f6de634e6b docs: add release notes for 23.1.4
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24281>
2023-07-21 15:53:50 +00:00
David Rosca
0bd9ab232b gallium/auxiliary/vl: Fix RGB->YCbCr full range matrix
Also rename it to bt_709_rev_full as there already
is bt_709 which is used for YCbCr->RGB.

Fixes: 8a21efce3a ("frontends/va: Add postproc support for converting to full range")

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24238>
2023-07-21 15:16:26 +00:00
Sathishkumar S
0195e1204b radeonsi/vcn: num bs_bufs must be proportional to num jpeg engines
using limited number of bs buffers constraints the simultaneous
use of all available jpeg engines especially when count is lesser than
that of the available engines. make sure the number of buffers
available are more than or equal to the number of jpeg engines on the asic.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24240>
2023-07-21 14:42:09 +00:00
Sathishkumar S
47a9d01641 radeonsi/vcn: support variable number of bs_bufs
add support to use variable number of bitstream buffers for decode

v2: remove the always true if condition (CI report)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24240>
2023-07-21 14:42:09 +00:00
Samuel Pitoiset
53d35c641d radv: bind the pre-compiled PS epilog to the cmdbuf state
For PS epilogs we have two paths, the first one is to pre-compile PS
epilogs at pipeline creation time, while the second one is to compile
PS epilogs on-demand when some dynamic states are used.

Binding the pre-compiled PS epilog to the cmdbuf state allows us to
remove one more pipeline dependency when recording cmdbufs (for shader
objects).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24254>
2023-07-21 12:55:30 +00:00
Samuel Pitoiset
55f05309ca radv: pass a shaders array for computing ia_multi_vgt_param
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24251>
2023-07-21 12:19:28 +00:00
Samuel Pitoiset
b0f53c3a48 radv: remove unused param in radv_pipeline_emit_vgt_gs_out()
Also rename the function.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24251>
2023-07-21 12:19:28 +00:00
Samuel Pitoiset
3348cd3a80 radv: stop using a pipeline for emitting VGT_VERTEX_REUSE_BLOCK_CNTL
Passing a TES is enough.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24251>
2023-07-21 12:19:28 +00:00
Alyssa Rosenzweig
03b2c34793 nir: Remove register arrays
Nothing produces them any more, so remove them from NIR. This massively reduces
the size of nir_src, which should improve performance all over.

nir_src size reduced from 56 bytes -> 40 bytes (pahole results on arm64, x86_64
should be similar.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>
2023-07-21 11:25:49 +00:00
Alyssa Rosenzweig
1466014184 nir: Rename lower_locals_to_reg_intrinsics back
The short name is freed up.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>
2023-07-21 11:25:49 +00:00
Alyssa Rosenzweig
d2c94f9e71 nir: Remove nir_lower_locals_to_regs
No more users, all switched to the intrinsic version.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>
2023-07-21 11:25:49 +00:00
Alyssa Rosenzweig
a8c0b6695f panfrost: Remove unused helpers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>
2023-07-21 11:25:48 +00:00
Alyssa Rosenzweig
a08286f993 intel/fs: Don't read reg.base_offset
It's not set in the new intrinsics path.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>
2023-07-21 11:25:48 +00:00
Rohan Garg
01965a2fe9 anv: drop CFE state validation checks
anv no longer needs to track if the CFE state is valid since we ensure
that the state is valid at pipeline creation time.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23934>
2023-07-21 10:46:08 +00:00
Rohan Garg
e7e7042093 anv,iris: program the maximum number of threads on compute queue init
Fixes: 90a39cac87 ("intel/blorp: Emit compute program based on BLORP_BATCH_USE_COMPUTE")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23934>
2023-07-21 10:46:08 +00:00
Christian Gmeiner
5a95280748 etnaviv: nir: lower nir_texop_txs
Non of the GPU models know at this time have hardware support to
retrieve the dimensions of a level of a texture. Do almost the
same as the binary blob and store the needed values as uniforms.

Passes dEQP-GLES3.functional.shaders.texture_functions.texturesize.*

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
Christian Gmeiner
88f399b651 etnaviv: nir: support intrinsic used for txs lowering
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
Christian Gmeiner
fb48d3d1da nir: add enta specific intrinsic used for txs lowering
Non of the know etnaviv GPUs support this feature in hardware
and the binary blob provides sizes via uniforms too.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
Christian Gmeiner
65ffa5b0b8 etnaviv: move nir texture lowerings into one pass
This is just a prep commit to keep all texture related
lowerings in one c file.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
Marcin Ślusarz
06046a02f8 anv: merge cases leading to the same code
Added in: 688968e888 ("anv: add support for direct descriptor in allocation/writes")

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24260>
2023-07-21 07:22:22 +00:00
Marcin Ślusarz
0eb2679cdb anv: drop unused function
Added in: 02cecffe2b ("anv: add a pass to partially lower resource_intel")

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24260>
2023-07-21 07:22:22 +00:00
Marcin Ślusarz
3c83ac8002 intel/compiler: remove redundant code
has_lsc is checked few lines above, so this code doesn't matter.

Added in: a358b97c58 ("intel/fs: optimize uniform SSBO & shared loads")

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24260>
2023-07-21 07:22:22 +00:00
Hyunjun Ko
e3ecba3266 anv: use ycbcr_info for P010 format
Since !24096 landed, we can just use ycbcr_info to get information
of an image of the P010 format.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24265>
2023-07-21 06:15:30 +00:00