Commit graph

20007 commits

Author SHA1 Message Date
Samuel Pitoiset
e8710152fb ac/nir: stop passing radeon_info for addr->coord helpers
Only for gb_addr_config.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40041>
2026-02-26 07:21:06 +00:00
Georg Lehmann
8f4de30d05 aco/insert_fp_mode: don't skip setting round for fract
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fract(-FLT_MIN) is < 1.0 with rtz but 1.0 with rtne.

Fixes: 7212a75c5e ("aco/insert_fp_mode: exclude some instructions that will never round")

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40078>
2026-02-26 00:20:02 +00:00
Samuel Pitoiset
52aaf307df radv: use radv_physical_cache_key::clear_lds more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40088>
2026-02-25 20:28:44 +00:00
Samuel Pitoiset
229e892e42 radv: use radv_physical_cache_key::disable_shrink_image_store more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40088>
2026-02-25 20:28:44 +00:00
Samuel Pitoiset
55691035e8 radv: use radv_physical_cache_key::disable_aniso_single_level more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40088>
2026-02-25 20:28:43 +00:00
Samuel Pitoiset
f045c04b50 radv: use radv_physical_cache_key::disable_trunc_coord more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40088>
2026-02-25 20:28:43 +00:00
Samuel Pitoiset
d7447012ef radv/nir: use radv_physical_cache_key::bvh8 more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40088>
2026-02-25 20:28:43 +00:00
Samuel Pitoiset
1457c39f5a radv/nir: use radv_physical_cache_key::emulate_rt more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40088>
2026-02-25 20:28:43 +00:00
Samuel Pitoiset
246b8501ce radv/nir: use radv_physical_cache_key::no_rt more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40088>
2026-02-25 20:28:41 +00:00
Benjamin Cheng
f8f80c3700 ac/parse_ib: Fix VCN address parsing
Some VCN IB packages (namely the common ops) put the address with the lo
part first.

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40068>
2026-02-25 16:59:31 +00:00
Ruijing Dong
f8eef1024c ac/vcn: correct a typo in av1 dec header
Correct a typo in AV1 frame header definition.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37650>
2026-02-25 09:02:28 +00:00
Samuel Pitoiset
c4d5090d69 radv: fix potential GPU hangs with secondaries on transfer queue
Cache flushes should be skipped on SDMA. In practice,
radv_emit_cache_flush() should only be called on GFX/ACE.

SDMA NOP packets are emitted in barriers directly.

This fixes recent VKCTS coverage
dEQP-VK.api.command_buffers.secondary_on_transfer_queue.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39964>
2026-02-25 08:16:57 +01:00
Samuel Pitoiset
2eb9420061 ac/nir: fix writemask for dual source blending on GFX11+
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This should definitely be an OR operation if MRT0 and MRT1 don't write
the same channels. This also requires to set the writemask manually
because when it's 0 (in case a dual-source output is missing), the
intrinsic computes the mask itself with the number of components.

No fossils-db changes on NAVI33.

Fixes: 45d8cd037a ("ac/nir: rewrite ac_nir_lower_ps epilog to fix dual src blending with mono PS")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14878
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39996>
2026-02-24 20:20:02 +00:00
Rhys Perry
05586fae67 radv: combine v_mov_dpp into fma in frag_coord.z adjust
This wasn't possible before because of the literal.

fossil-db (vangogh):
Totals from 3766 (3.36% of 112041) affected shaders:
Instrs: 5646975 -> 5642967 (-0.07%); split: -0.09%, +0.02%
CodeSize: 30751152 -> 30749956 (-0.00%); split: -0.02%, +0.02%
VGPRs: 262640 -> 262672 (+0.01%); split: -0.01%, +0.02%
Latency: 184869423 -> 184883681 (+0.01%); split: -0.02%, +0.03%
InvThroughput: 43462111 -> 43456113 (-0.01%); split: -0.03%, +0.02%
VClause: 93337 -> 93353 (+0.02%); split: -0.10%, +0.12%
SClause: 186857 -> 186833 (-0.01%); split: -0.07%, +0.06%
Copies: 390583 -> 390327 (-0.07%); split: -0.44%, +0.38%
Branches: 106070 -> 106086 (+0.02%); split: -0.03%, +0.05%
VALU: 4112856 -> 4108839 (-0.10%); split: -0.12%, +0.02%
SALU: 593814 -> 593758 (-0.01%); split: -0.05%, +0.04%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40013>
2026-02-24 18:34:38 +00:00
Rhys Perry
437a3d5ade radv: disable fast math for frag_coord.z adjust
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40013>
2026-02-24 18:34:37 +00:00
Caterina Shablia
5e25953690 radv: move all image checks into radv_image_need_retile
There's no reason to have these checks be smeared between
radv_image_need_retile and radv_retile_transition.

Make radv_image_need_retile verify that the image might ever
need to have its displayable DCC updated.

Also, radv_image_need_retile should not care about the command
buffer. We should never try to do retile transition on a
command buffer that can't do compute to begin with.

Make radv_retile_transition only check whether the layout
we're transitioning to might involve reading the displayable
DCC, and perform retiling if so.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39990>
2026-02-24 18:08:53 +00:00
Caterina Shablia
4529be010b radv: skip retiling if transitioning away from ZERO_INITIALIZED
Zeros are already a sensible value for display DCC metadata
to have and correctly represent a zeroed image.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39990>
2026-02-24 18:08:53 +00:00
Rhys Perry
613b4fe407 aco: resolve hazards before calls
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 26.0
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39825>
2026-02-24 13:20:55 +00:00
Rhys Perry
dfda890ae8 aco: reset all vgpr_used_by_vmem_ in resolve_all_gfx11
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 26.0
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39825>
2026-02-24 13:20:55 +00:00
Rhys Perry
72923ad2f0 aco: fix VALUReadSGPRHazard with s_call_b64/s_swappc_b64
This probably doesn't do anything because sgpr_read_by_valu are all set
already for raytracing shaders.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39825>
2026-02-24 13:20:54 +00:00
Benjamin Cheng
2bb26573e7 radv/video: Split cdf buffer and encode ctx
These resources are fundamentally different and should be treated as
such.

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40050>
2026-02-24 12:29:25 +00:00
Samuel Pitoiset
755cb6cb75 radv: fix independent sets with dynamic buffers and GPL
If a set layout is missing the driver can't compute the dynamic buffer
start offsets correctly. The only solution is to load these offsets from
an user SGPR.

To avoid adding more complexity, these offsets are re-emitted every
time dynamic buffers are dirty. That shouldn't matter because the
combination of dynamic buffers and independent sets is just super rare.

This fixes new VKCTS coverage
dEQP-VK.pipeline.pipeline_library.graphics_library.independent_sets_random.*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39988>
2026-02-24 11:12:14 +00:00
Georg Lehmann
c6e1c23faf radv: expose VK_VALVE_shader_mixed_float_dot_product on supported hardware
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In practice this means Vega20, Navi14, and RDNA2+.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40003>
2026-02-24 08:55:53 +00:00
Georg Lehmann
892274d20d ac/llvm: implement mixed float dot
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40003>
2026-02-24 08:55:53 +00:00
Georg Lehmann
dd067088ef aco: allow dpp for fp8/bf8 dot4
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40003>
2026-02-24 08:55:53 +00:00
Georg Lehmann
a033cd95a4 aco: allow modifiers for fp16 dot
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40003>
2026-02-24 08:55:53 +00:00
Georg Lehmann
3238e64d3c aco/ra: create v_dot2c_f32_f16
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40003>
2026-02-24 08:55:53 +00:00
Georg Lehmann
237b8ca205 aco: mixed float dot product opcodes
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40003>
2026-02-24 08:55:52 +00:00
Samuel Pitoiset
06949b74eb radv: suspend/resume dynamic rendering completely
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The Vulkan spec says:
    "The contents of pRenderingInfo must match between suspended
     render pass instances and the render pass instances that resume
     them, other than the presence or absence of the0
     VK_RENDERING_RESUMING_BIT, VK_RENDERING_SUSPENDING_BIT, and
     VK_RENDERING_CONTENTS_SECONDARY_COMMAND_BUFFERS_BIT flags. No
     action or synchronization commands, or other render pass
     instances, are allowed between suspending and resuming render
     pass instances. All pairs of resuming and suspending render passes
     must be submitted in the same batch. "

So it should be safe to avoid re-emitting the rendering state because
nothing can blow it up.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40004>
2026-02-24 07:33:28 +00:00
Samuel Pitoiset
e6523feed9 radv: handle the cache flush workaround for mips before emitting the fb
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40004>
2026-02-24 07:33:28 +00:00
Samuel Pitoiset
cc08a1594e radv: skip some redundant operations when rendering is resumed
No need to do it twice, and nothing can blow it up between
suspend/resume rendering operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40004>
2026-02-24 07:33:28 +00:00
Samuel Pitoiset
d45586f1c0 radv: reserve CS space for the HiZ WA on GFX12
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40004>
2026-02-24 07:33:28 +00:00
Samuel Pitoiset
ab6147e8ef radv/meta: fix depth/stencil resolves with different regions
This is possible since VK_KHR_maintenance10.

This fixes new VKCTS coverage in
dEQP-VK.pipeline.*.multisample.m10_resolve.*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39956>
2026-02-24 07:09:17 +00:00
Natalie Vock
b08f9f192c radv/nir: Correctly handle workgroup sizes not aligned to 32
Since the stride is always 32 dwords, we need to treat the workgroup
size as multiples of that value. Using MAX2() only works for cases where
the workgroup size is less than 32, which was hit by some CTS with 1x1
workgroups.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39981>
2026-02-23 12:42:24 +00:00
Samuel Pitoiset
7d03a1fc5b radv: skip some operations when the image is already zero-initialized
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No need to clear to zero because it should already be cleared.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40012>
2026-02-23 09:06:21 +00:00
Samuel Pitoiset
837078b8d5 radv: fix potential corruption after FMASK decompression on GFX6-8
While reworking image resolves completely in RADV, I found a very weird
bug where the only fix was to emit caches immediately after
decompressing the source resolve image (after FMASK_DECOMPRESS).

I have been struggling this for few hours and figured that it was
something related to context rolls (ie. as long the context was rolled
out, emitting the flushes immediately was required).

It turns out this was a known hardware bug on GFX6 that was implemented
in PAL. Though PAL only applies on GFX6 but GFX7-8 are also affected
based on my testing. Note that RadeonSI flushes CB_META too.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39959>
2026-02-23 08:32:53 +00:00
Rhys Perry
af27fb23f3 aco/ra: don't modify parallelcopies if get_reg_for_affinity fails
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Fixes baldurs_gate_3/60c8b7ff623fbb18 with vega10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 310f588f92 ("aco/ra: move variables from affinity register to avoid waitcnt")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39986>
2026-02-20 08:40:55 +00:00
Rhys Perry
75722da909 aco: fix gfx6-8 store_scratch() with function calls
Might happen with radv_emulate_rt=true.

Fixes the_great_circle/a6079328b8df7712 with polaris10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: e006f68b11 ("aco/isel: Don't add scratch offset as gfx8- soffset if no offsets exist")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39986>
2026-02-20 08:40:55 +00:00
David Rosca
0d7117f0d7 ac/vcn_dec: Fix tier2 dpb array size
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In some cases, this would incorrectly set higher dpbArraySize
when overwriting already existing dpb slot.
This didn't seem to cause any issues, but the extra slot would
have zero va which was wrong.
Get the actual ref count from codec param, instead of using
cmd->num_refs which always includes current slot. Also add sanity
check that the ref surface was found.

Fixes: 79af03556c ("ac: Add VCN ac_video_dec implementation")
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39877>
2026-02-19 12:24:29 +00:00
Samuel Pitoiset
8b5296b01c radv: simplify buffer-to-image and image-to-image operations for 96-bit formats
It's possible to use the existing shaders with a small tweak. This
removes a bunch of code in meta.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39935>
2026-02-19 07:12:47 +00:00
Natalie Vock
47e4a68a83 radv: Initialize nir_lower_io_to_scalar progress variable
The NIR_PASS macro only overwrites this when the pass actually makes
progress. If the pass doesn't make progress, the variable stays
uninitialized.

Clang correctly spots this and warns about it.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39968>
2026-02-18 21:44:49 +00:00
Natalie Vock
59a397793e radv/rt: Only use ds_bvh_stack_rtn if the stack base is possible to encode
The hardware only provides 13 bits for encoding the stack base (in
dwords). That translates to the stack base being required to be below
8192 dwords, or 32kB. It's possible to exceed this - LDS is 64kB after
all. Add an explicit check to make sure we don't end up with offsets
that overflow the hw's address fields. This fixes Metro Exodus Enhanced
Edition, which was using ray queries in a 1024-thread sized workgroup,
resulting in exactly 64kB of LDS being required for the stack.

This check isn't required for RT pipelines as we always use 32 or 64
wide workgroups with no other LDS used, so it's impossible to reach this
stack base limit.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39691>
2026-02-18 19:12:18 +00:00
Konstantin Seurer
ae84d41d48 radv/meta: Rework saving/restoring state
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The current approach of explicitly saving/restoring some states is
unnecessarily complicated and inefficient. For example, some meta OPs
that use memory fills/copies will have nested save/restores. This patch
is the first step towards avoiding unnecessary state re-emits around
meta OPs.

The changes are:
- Move radv_meta_saved_state to radv_cmd_buffer::state
- Add radv_meta_begin/end helpers that initialize radv_meta_saved_state
and restore states used by the meta OP
- Remove all explicit saves/restores, use the new helpers

radv_meta_begin/end is called inside the entrypoint and not some nested
helper function which means that state is only restored once per meta
OP.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39774>
2026-02-18 09:37:55 +01:00
Konstantin Seurer
d3cb2978b8 radv/meta: Add and use helpers for setting state
It's less code and allows the next commit to track which states a meta
command uses.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39774>
2026-02-18 09:37:30 +01:00
Samuel Pitoiset
090b67a163 vulkan/runtime: add support for ETC2 emulation with copy_memory_indirect
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39908>
2026-02-18 07:04:43 +00:00
Priya Hosur
0bfad39f15 ac/nir/ngg: re-enable use of known compile-time GS connectivity
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38075>
2026-02-18 01:29:37 +00:00
Marek Olšák
a2309edb6b ac/nir/meta: properly align sparse buffer clears with 12-byte clear values
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39841>
2026-02-17 14:47:41 +00:00
Marek Olšák
62cce3abcd ac/nir/meta: use the clear/copy compute shader if CP DMA doesn't support sparse
ac_prepare_cs_clear_copy_buffer determines whether to use CP DMA, and
the driver obeys that.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39841>
2026-02-17 14:47:41 +00:00
Marek Olšák
bbcfab9f4f ac/nir/meta: don't scalarize sparse loads if the address is aligned to load size
This should make copying sparse faster if we get aligned buffer bounds.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39841>
2026-02-17 14:47:41 +00:00
Samuel Pitoiset
95c4d8d726 radv/meta: rework get_image_stride_for_96bit() and make it non-static
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macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39909>
2026-02-17 10:39:01 +00:00