fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-03-12 11:10:34 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 3

ac/nir: stop passing radeon_info for addr->coord helpers

Browse source 
Only for gb_addr_config.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40041>
This commit is contained in:
Samuel Pitoiset 2026-02-23 14:43:31 +01:00 • committed by Marge Bot
parent 63e1592f8d
commit e8710152fb
4 changed files with 40 additions and 34 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

38
src/amd/common/nir/ac_nir_surface.c
View file

@ -9,7 +9,7 @@
#include "nir_builder.h"
#include "sid.h"
static nir_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info,
static nir_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, uint32_t gb_addr_config,
const struct gfx9_meta_equation *equation,
int blkSizeBias, unsigned blkStart,
nir_def *meta_pitch, nir_def *meta_slice_size,
@ -20,8 +20,6 @@ static nir_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct rade
nir_def *zero = nir_imm_int(b, 0);
nir_def *one = nir_imm_int(b, 1);
assert(info->gfx_level >= GFX10);
unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width);
unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height);
unsigned blkSizeLog2 = meta_block_width_log2 + meta_block_height_log2 + blkSizeBias;
@ -47,8 +45,8 @@ static nir_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct rade
}
unsigned blkMask = (1 << blkSizeLog2) - 1;
unsigned pipeMask = (1 << G_0098F8_NUM_PIPES(info->gb_addr_config)) - 1;
unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
unsigned pipeMask = (1 << G_0098F8_NUM_PIPES(gb_addr_config)) - 1;
unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(gb_addr_config);
nir_def *xb = nir_ushr_imm(b, x, meta_block_width_log2);
nir_def *yb = nir_ushr_imm(b, y, meta_block_height_log2);
nir_def *pb = nir_ushr_imm(b, meta_pitch, meta_block_width_log2);
@ -64,7 +62,7 @@ static nir_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct rade
nir_ixor(b, nir_ushr(b, address, one), pipeXor));
}
static nir_def *gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info,
static nir_def *gfx9_nir_meta_addr_from_coord(nir_builder *b, uint32_t gb_addr_config,
const struct gfx9_meta_equation *equation,
nir_def *meta_pitch, nir_def *meta_height,
nir_def *x, nir_def *y, nir_def *z,
@ -74,13 +72,11 @@ static nir_def *gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct radeo
nir_def *zero = nir_imm_int(b, 0);
nir_def *one = nir_imm_int(b, 1);
assert(info->gfx_level >= GFX9);
unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width);
unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height);
unsigned meta_block_depth_log2 = util_logbase2(equation->meta_block_depth);
unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(gb_addr_config);
unsigned numPipeBits = equation->u.gfx9.num_pipe_bits;
nir_def *pitchInBlock = nir_ushr_imm(b, meta_pitch, meta_block_width_log2);
nir_def *sliceSizeInBlock = nir_imul(b, nir_ushr_imm(b, meta_height, meta_block_height_log2),
@ -131,27 +127,29 @@ static nir_def *gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct radeo
nir_ishl_imm(b, pipeXor, m_pipeInterleaveLog2));
}
nir_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
nir_def *ac_nir_dcc_addr_from_coord(nir_builder *b, enum amd_gfx_level gfx_level,
uint32_t gb_addr_config,
unsigned bpe, const struct gfx9_meta_equation *equation,
nir_def *dcc_pitch, nir_def *dcc_height,
nir_def *dcc_slice_size,
nir_def *x, nir_def *y, nir_def *z,
nir_def *sample, nir_def *pipe_xor)
{
if (info->gfx_level >= GFX10) {
if (gfx_level >= GFX10) {
unsigned bpp_log2 = util_logbase2(bpe);
return gfx10_nir_meta_addr_from_coord(b, info, equation, bpp_log2 - 8, 1,
return gfx10_nir_meta_addr_from_coord(b, gb_addr_config, equation, bpp_log2 - 8, 1,
dcc_pitch, dcc_slice_size,
x, y, z, pipe_xor, NULL);
} else {
return gfx9_nir_meta_addr_from_coord(b, info, equation, dcc_pitch,
return gfx9_nir_meta_addr_from_coord(b, gb_addr_config, equation, dcc_pitch,
dcc_height, x, y, z,
sample, pipe_xor, NULL);
}
}
nir_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info,
nir_def *ac_nir_cmask_addr_from_coord(nir_builder *b, enum amd_gfx_level gfx_level,
uint32_t gb_addr_config,
const struct gfx9_meta_equation *equation,
nir_def *cmask_pitch, nir_def *cmask_height,
nir_def *cmask_slice_size,
@ -161,25 +159,27 @@ nir_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *
{
nir_def *zero = nir_imm_int(b, 0);
if (info->gfx_level >= GFX10) {
return gfx10_nir_meta_addr_from_coord(b, info, equation, -7, 1,
if (gfx_level >= GFX10) {
return gfx10_nir_meta_addr_from_coord(b, gb_addr_config, equation, -7, 1,
cmask_pitch, cmask_slice_size,
x, y, z, pipe_xor, bit_position);
} else {
return gfx9_nir_meta_addr_from_coord(b, info, equation, cmask_pitch,
return gfx9_nir_meta_addr_from_coord(b, gb_addr_config, equation, cmask_pitch,
cmask_height, x, y, z, zero,
pipe_xor, bit_position);
}
}
nir_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info,
nir_def *ac_nir_htile_addr_from_coord(nir_builder *b, enum amd_gfx_level gfx_level,
uint32_t gb_addr_config,
const struct gfx9_meta_equation *equation,
nir_def *htile_pitch,
nir_def *htile_slice_size,
nir_def *x, nir_def *y, nir_def *z,
nir_def *pipe_xor)
{
return gfx10_nir_meta_addr_from_coord(b, info, equation, -4, 2,
assert(gfx_level >= GFX10);
return gfx10_nir_meta_addr_from_coord(b, gb_addr_config, equation, -4, 2,
htile_pitch, htile_slice_size,
x, y, z, pipe_xor, NULL);
}

9
src/amd/common/nir/ac_nir_surface.h
View file

@ -16,14 +16,16 @@
extern "C" {
#endif
nir_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
nir_def *ac_nir_dcc_addr_from_coord(nir_builder *b, enum amd_gfx_level gfx_level,
uint32_t gb_addr_config,
unsigned bpe, const struct gfx9_meta_equation *equation,
nir_def *dcc_pitch, nir_def *dcc_height,
nir_def *dcc_slice_size,
nir_def *x, nir_def *y, nir_def *z,
nir_def *sample, nir_def *pipe_xor);
nir_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info,
nir_def *ac_nir_cmask_addr_from_coord(nir_builder *b, enum amd_gfx_level gfx_level,
uint32_t gb_addr_config,
const struct gfx9_meta_equation *equation,
nir_def *cmask_pitch, nir_def *cmask_height,
nir_def *cmask_slice_size,
@ -31,7 +33,8 @@ nir_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *
nir_def *pipe_xor,
nir_def **bit_position);
nir_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info,
nir_def *ac_nir_htile_addr_from_coord(nir_builder *b, enum amd_gfx_level gfx_level,
uint32_t gb_addr_config,
const struct gfx9_meta_equation *equation,
nir_def *htile_pitch,
nir_def *htile_slice_size,

18
src/amd/vulkan/nir/radv_meta_nir.c
View file

@ -894,9 +894,9 @@ radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, const stru
/* Get the HTILE addr from coordinates. */
nir_def *zero = nir_imm_int(&b, 0);
nir_def *htile_offset =
ac_nir_htile_addr_from_coord(&b, &pdev->info, &surf->u.gfx9.zs.htile_equation, htile_pitch, htile_slice_size,
nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero);
nir_def *htile_offset = ac_nir_htile_addr_from_coord(
&b, pdev->info.gfx_level, pdev->info.gb_addr_config, &surf->u.gfx9.zs.htile_equation, htile_pitch,
htile_slice_size, nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero);
/* Set up the input VRS image descriptor. */
const struct glsl_type *vrs_sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_FLOAT);
@ -982,12 +982,12 @@ radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, const str
coord =
nir_imul(&b, coord, nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, surf->u.gfx9.color.dcc_block_height));
nir_def *src = ac_nir_dcc_addr_from_coord(&b, &pdev->info, surf->bpe, &surf->u.gfx9.color.dcc_equation,
src_dcc_pitch, src_dcc_height, zero, nir_channel(&b, coord, 0),
nir_channel(&b, coord, 1), zero, zero, zero);
nir_def *dst = ac_nir_dcc_addr_from_coord(&b, &pdev->info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
dst_dcc_pitch, dst_dcc_height, zero, nir_channel(&b, coord, 0),
nir_channel(&b, coord, 1), zero, zero, zero);
nir_def *src = ac_nir_dcc_addr_from_coord(&b, pdev->info.gfx_level, pdev->info.gb_addr_config, surf->bpe,
&surf->u.gfx9.color.dcc_equation, src_dcc_pitch, src_dcc_height, zero,
nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero, zero);
nir_def *dst = ac_nir_dcc_addr_from_coord(
&b, pdev->info.gfx_level, pdev->info.gb_addr_config, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
dst_dcc_pitch, dst_dcc_height, zero, nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero, zero);
nir_def *dcc_val = nir_image_deref_load(&b, 1, 32, input_dcc_ref, nir_vec4(&b, src, src, src, src),
nir_undef(&b, 1, 32), nir_imm_int(&b, 0), .image_dim = dim,

9
src/gallium/drivers/radeonsi/si_shaderlib_nir.c
View file

@ -67,7 +67,8 @@ void *si_create_dcc_retile_cs(struct si_context *sctx, const struct radeon_surf
surf->u.gfx9.color.dcc_block_height));
nir_def *src_offset =
ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.dcc_equation,
ac_nir_dcc_addr_from_coord(&b, sctx->screen->info.gfx_level, sctx->screen->info.gb_addr_config,
surf->bpe, &surf->u.gfx9.color.dcc_equation,
src_dcc_pitch, src_dcc_height, zero, /* DCC slice size */
nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), /* x, y */
zero, zero, zero); /* z, sample, pipe_xor */
@ -75,7 +76,8 @@ void *si_create_dcc_retile_cs(struct si_context *sctx, const struct radeon_surf
nir_def *value = nir_load_ssbo(&b, 1, 8, zero, src_offset, .align_mul=1);
nir_def *dst_offset =
ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
ac_nir_dcc_addr_from_coord(&b, sctx->screen->info.gfx_level, sctx->screen->info.gb_addr_config,
surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
dst_dcc_pitch, dst_dcc_height, zero, /* DCC slice size */
nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), /* x, y */
zero, zero, zero); /* z, sample, pipe_xor */
@ -112,7 +114,8 @@ void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *
tex->surface.u.gfx9.color.dcc_block_depth));
nir_def *offset =
ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, tex->surface.bpe,
ac_nir_dcc_addr_from_coord(&b, sctx->screen->info.gfx_level,
sctx->screen->info.gb_addr_config, tex->surface.bpe,
&tex->surface.u.gfx9.color.dcc_equation,
dcc_pitch, dcc_height, zero, /* DCC slice size */
nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), /* x, y */