Commit graph

3994 commits

Author SHA1 Message Date
Rhys Perry
524848707b radv: don't set sx_blend_opt_epsilon for V_028C70_COLOR_10_11_11
Matches radeonsi and PAL. From PAL:
// 1 is recommended, but doesn't provide sufficient precision

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4394
Fixes: ed94638156 ("radv: Enable RB+ where possible.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9427>
2021-03-05 11:16:40 +00:00
Samuel Pitoiset
2169c4f763 radv: re-enable TC-compat HTILE for MSAA D32S8 images on GFX9+
Should help MSAA games. Note that it's broken on GFX8 because
the tiling doesn't match.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3868
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9284>
2021-03-05 08:44:40 +00:00
Samuel Pitoiset
367a93830b radv: skip useless FCE when fast-clearing MSAA images with DCC enabled
The clear code is 0xCC which means CMASK isn't fast-cleared.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9392>
2021-03-05 08:11:28 +00:00
Samuel Pitoiset
6102507a74 radv: remove useless check about mips+layers for TC-compat HTILE images
radv_use_htile_for_image() prevents it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9405>
2021-03-05 08:10:19 +01:00
Samuel Pitoiset
438f65fb1e radv: cleanup enabling TC-compat HTILE for depth surfaces
It makes more sense to try to enable TC-compat if the image has HTILE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9405>
2021-03-05 08:09:42 +01:00
Samuel Pitoiset
517600b4d5 Revert "radv: stop using VM_ALWAYS_VALID on APUs"
Disabling VM_ALWAYS_VALID actually hurts more than it helps
after doing more testing. Managing the global BO list in userspace
is really costly and make a bunch of games CPU bound.

I think re-enabling VM_ALWAYS_VALID is a step in the right direction.

This reverts commit 6ac6e2fbfb.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9341>
2021-03-04 09:37:59 +00:00
Marek Olšák
18c1c1404d ac/llvm: add type parameter into ac_build_buffer_load to fix 16-bit TES inputs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9395>
2021-03-03 20:06:09 +00:00
Samuel Pitoiset
578fc7dbbc radv: fix RGP barrier layout transition for TC-compatible CMASK images
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9390>
2021-03-03 16:49:29 +00:00
Rhys Perry
21697082ec radv: don't shrink image stores for The Surge 2
The game seems to declare the wrong format.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: e4d75c22 ("nir/opt_shrink_vectors: shrink image stores using the format")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4347
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9229>
2021-03-03 14:18:37 +00:00
Rhys Perry
cbb5ed476c nir/opt_shrink_vectors: add option to skip shrinking image stores
Some games declare the wrong format, so we might want to disable this
optimization in that case.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: e4d75c22 ("nir/opt_shrink_vectors: shrink image stores using the format")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9229>
2021-03-03 14:18:37 +00:00
Samuel Pitoiset
b33792b794 radv: bump the initial SQTT buffer size to 32MB per SE
Most of the games need 32MB or more, but rarely less.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9367>
2021-03-03 08:40:32 +01:00
Samuel Pitoiset
6813b52290 radv: trigger a new SQTT capture automatically after resizing the buffer
It's way better.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9367>
2021-03-03 08:40:32 +01:00
Samuel Pitoiset
0a1e3cc1cb radv: double the SQTT buffer size when it is resized
Computing the expected buffer size isn't reliable on GFX10+ because
DROPPED_CNTR returns weird results.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9367>
2021-03-03 08:40:32 +01:00
Samuel Pitoiset
c0608bb083 ac/sqtt: fix determining if the trace is complete on GFX10+
DROPPED_CNTR isn't reliable and might still report non-zero if the
SQTT buffer isn't full. Checking if the number of written bytes by
the hw is equal to the SQTT buffer size seems reliable.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9367>
2021-03-03 08:40:32 +01:00
Samuel Pitoiset
f4c4c0f207 radv: do not trace inactive shader engines with SQTT
This fixes a GPU hang on my Sienna because the number of SE is
less than the maximum, and SE #1 is disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9370>
2021-03-03 08:16:42 +01:00
Rhys Perry
941739619e Revert "radv,aco: allow unaligned LDS access on GFX9+"
This reverts commit 1a0b0e8460.

The bounds checking behaviour of ds_read_b64, ds_read_b96 and ds_read_b128
make this feature very difficult to use safely.

This fixes a blocking artifact in Hitman 2. Previously, it contained:
ds_read_b64(local_invocation_index() * 4 - 4)
For local_invocation_index()=0, the second dword would be considered
out-of-bounds, even though it's at offset 0.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9332>
2021-03-02 13:13:59 +00:00
Samuel Pitoiset
97925cee8d radv: remove useless decompression of the DS resolve attachment
The DS resolve attachment is the destination attachment, it doesn't
need to be decompressed before resolving the depth/stencil attachment.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9256>
2021-03-01 18:10:35 +00:00
Bas Nieuwenhuizen
ff99faf0cf radv: Add nodisplaydcc option.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9318>
2021-03-01 14:42:41 +00:00
Bas Nieuwenhuizen
3c9452c3ae radv: Add sam option.
So that people without large BAR can try this out.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9318>
2021-03-01 14:42:41 +00:00
Bas Nieuwenhuizen
0360ecac73 radv: Enable linear sampling for depth textures.
Turns out there are CTS tests.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4258
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9319>
2021-03-01 13:14:09 +00:00
Samuel Pitoiset
56bff270fe radeonsi,radv: do not overallocate the SQTT buffer size
The number of shader engines isn't always 4.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9307>
2021-03-01 13:13:36 +01:00
Samuel Pitoiset
24f015eddc Revert "radv: do not overallocate the SQTT buffer"
This fixes computing the thread trace data offset.

This reverts commit c7e6f4ff3d.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9307>
2021-03-01 13:09:15 +01:00
Samuel Pitoiset
6b53f7f969 radv: exclude perf counters for SQTT also on GFX10.3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9300>
2021-03-01 11:20:19 +00:00
Samuel Pitoiset
859dbf953d radv: fix exporting SQTT pipelines with LLVM
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9300>
2021-03-01 11:20:19 +00:00
Samuel Pitoiset
d26bcc0f5c radv: always select the first active CU when profiling with SQTT
This probably fixes instruction tracing on many chips.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9300>
2021-03-01 11:20:19 +00:00
Samuel Pitoiset
b511bf262d radv: remove duplicate REG_INCLUDE_CONTEXT setting for SQTT
It was set twice.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9300>
2021-03-01 11:20:19 +00:00
Bas Nieuwenhuizen
f67259d83b radv: Expose robustBufferAccessUpdateAfterBind correctly.
We do support it.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4351
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9281>
2021-02-26 23:53:52 +00:00
Samuel Pitoiset
8a47422d97 radv: do not scale the depth bias for D16_UNORM depth surfaces
Scaling the depth bias doesn't seem correct with Vulkan. This is
probably the root cause of the shadow artifacts differences between
RADV and AMDVLK/AMDGPU-PRO.

Fix dEQP-VK.rasterization.depth_bias.d16_unorm.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2217
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9249>
2021-02-25 08:17:27 +01:00
Mike Blumenkrantz
6875e10350 radv: for_each_bit -> foreach_bit
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9191>
2021-02-24 17:11:44 +00:00
Bas Nieuwenhuizen
d7e1f492bc radv: Disable displayable DCC for GFX8 properly.
On scanout the GFX8 ac_surface doesn't clear the size but only
doesn't allocate space and hence dcc_offset is 0. This is the same
as radeonsi.

Fixes: 7acb30de8a ("radv: Enable displayable DCC.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4346
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9221>
2021-02-23 16:57:04 +00:00
Samuel Pitoiset
765097eac4 radv: add support for instruction timing with RGP
This is probably the most useful feature with SQTT/RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9130>
2021-02-23 13:03:39 +00:00
Samuel Pitoiset
a72b7a9b6c radv: add support for exporting pipelines with RGP
This is still experimental and only enabled with
RADV_THREAD_TRACE_PIPELINE to avoid breaking existing support.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9130>
2021-02-23 13:03:39 +00:00
Samuel Pitoiset
884e14d784 radv: store a pointer to the code in radv_shader_variant
This will be used by SQTT to dump the disassembly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9130>
2021-02-23 13:03:39 +00:00
Bas Nieuwenhuizen
7acb30de8a radv: Enable displayable DCC.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9042>
2021-02-23 13:32:42 +01:00
Bas Nieuwenhuizen
f848f2adfa radv: Use ac_surface DCC settings for shareable images.
On GFX10 the settings for displayable DCC are different than those
for normal texturing.

This is technically a slight pessimization as ac_surface does not
know about textures that don't have to be sampled. However, for color
surfaces this is a very unlikely situation as presumably even MSAA
images have to be resolved (potentially using texture HW).

So in practice this should be equal for everything except displayable DCC.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9042>
2021-02-23 13:32:36 +01:00
Bas Nieuwenhuizen
0e189dd3fd radv: Add DCC info to the metadata.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9042>
2021-02-23 13:32:33 +01:00
Bas Nieuwenhuizen
54f3ed224d radv: Implement displayable DCC retiling.
Straightforward implementation using the retile map from radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9042>
2021-02-23 13:32:29 +01:00
Bas Nieuwenhuizen
e34542bdf1 radv: Implement initialization of displayable DCC.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9042>
2021-02-23 13:32:26 +01:00
Bas Nieuwenhuizen
e59847f67f radv: Use shared code for setting opaque metadata.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9042>
2021-02-23 13:32:20 +01:00
Bas Nieuwenhuizen
9c5c995cbe radv: Handle UMD metadata on import.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9042>
2021-02-23 13:32:16 +01:00
Bas Nieuwenhuizen
2d520b6923 radv: Don't use dedicated memory info to indicate sharing.
Can be used without sharing, so if only the dedicated memory info
is set we know it isn't shareable. Use that.

Fixes: a639d40f13 ("radv: add support for local bos. (v3)")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4330
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9176>
2021-02-22 13:08:40 +00:00
Samuel Pitoiset
e5d8b731e4 radv: emit missing subpass resolve marker for SQTT
RGP now shows CmdEndRenderPassResolve() in the Event timing panel.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9106>
2021-02-22 08:30:38 +01:00
Samuel Pitoiset
491a1949eb radv: rework radv_cmd_buffer_resolve_subpass() a bit
To emit the subpass resolve marker properly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9106>
2021-02-22 08:30:36 +01:00
Dave Airlie
bd98fc39ae radv: reset object base on recycled command buffers
The loader_set_dispatch overwrites the magic with the dispatch
pointer, however when cmd buffers get recycled, and the loader
is in debug mode, it asserts that the magic isn't set anymore.

When recycling command buffers, reset the base object.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9145>
2021-02-22 09:32:45 +10:00
Yogesh Mohan Marimuthu
5d51ccd7d1 ac/rgp,radeonsi,radv: pass struct thread_trace_data to ac_sqtt_dump_data()
struct thread_trace_data holds struct rgp_code_object, struct
rgp_loader_events, struct rgp_pso_correlation data. This data is required
in function ac_sqtt_dump_data(). This patch makes the code changes
required to pass struct thread_trace_data to function ac_sqtt_dump_data().

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8609>
2021-02-19 14:29:47 +00:00
Samuel Pitoiset
88f42ea93e radv: emit the trap handler registers earlier
Directly into the GFX init IB.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9076>
2021-02-19 08:58:19 +00:00
Samuel Pitoiset
2c6104d3d1 radv: make the TMA/TBA BOs resident buffers
They are always used if the trap handler is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9076>
2021-02-19 08:58:19 +00:00
Samuel Pitoiset
918838cd24 radv: make the trace BO a resident buffer
It's always used if RADV_DEBUG=hang is set.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9076>
2021-02-19 08:58:19 +00:00
Samuel Pitoiset
d96c0a2263 radv: make the border color BO a resident buffer
It's always used if the feature is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9076>
2021-02-19 08:58:19 +00:00
Samuel Pitoiset
e3bdf815b7 radv: set correct value for OFFCHIP_BUFFERING on GFX10+
Higher values break tessellation. I was only able to reproduce this
by switching back/from AMDVLK which was really weird...

According to Marek (1c6eca23fd), it looks like it's related to
register shadowing and PAL enables it, that probably explains a bit.

Copied from PAL and RadeonSI.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4207
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2498
Fixes: 74d69299d1 ("radv/gfx10: double the number of tessellation offchip buffers per SE")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9141>
2021-02-19 08:52:26 +01:00