Commit graph

162020 commits

Author SHA1 Message Date
Mykhailo Skorokhodov
e4b7bf1a6d nir: Make lower_double_ops recognize SPIR-V mangling
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18854>
2022-10-28 10:08:50 +00:00
Mykhailo Skorokhodov
9786d9ef2a util: Add glsl2spirv.py script
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18854>
2022-10-28 10:08:50 +00:00
Nanley Chery
48844910a3 iris: Enable INTEL_MEASURE for compute dispatches on XeHP
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19324>
2022-10-28 09:28:01 +00:00
Lucas Stach
a41c0b58aa etnaviv: blt: try to find exact format match first
For MSAA downsampling to work correctly, the BLT engine needs to know
the exact format of the blit source/target. The compatible formats are
fine as long as the BLT is only used as a tiler without doing any
conversion.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19349>
2022-10-28 08:49:11 +00:00
Lucas Stach
0f34a092e4 etnaviv: blt: scale operations by MSAA mode
Same as with the RS engine, BLT operations need to be scaled by
the MSAA size.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19349>
2022-10-28 08:49:11 +00:00
Samuel Pitoiset
c41997f29f radv: fix suspending/resuming pipeline statistics queries with GDS
This probably doesn't fix anything in practice because GDS is only
used for the number of generated primitives by GS and meta operations
don't use GS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19348>
2022-10-28 08:12:30 +00:00
Samuel Pitoiset
cf687e88ce ac/nir/ngg: fix emitting streamout output by using packed location
In RadeonSI, they are packed but not in RADV, so don't rely on driver
locations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19365>
2022-10-28 07:49:32 +00:00
Lionel Landwerlin
920aed2121 intel/compiler: don't allocate compaction arrays on the stack
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7569
Cc: mesa-stable
Reviewed-by: Luis Felipe Strano Moraes <luis.strano@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19339>
2022-10-28 07:10:58 +00:00
Iago Toral Quiroga
29588fe116 v3dv: re-enable sync_fd import/export
Now that we implement GPU-side event functions in the GPU we
no longer have the issue that didn't allow us to expose
sync_fd.

Further more, new spec text has also made the problematic
behavior undefined, so the test that caused this issue,
dEQP-VK.api.external.semaphore.sync_fd.import_twice_temporary,
is incorrect and should be fixed.

It should be noted that we still keep sync_fd disabled in the
simulator, at least until the CTS tests are fixed, since the
synchronous execution model of the simulator means that in the
problematic scenario we can block the CPU on the execution
of the command buffer before we ever submit the signaling job,
still causing a deadlock.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19313>
2022-10-28 08:41:13 +02:00
Iago Toral Quiroga
ecb01d53fd v3dv: refactor events
This replaces our current implementation, which is 100% CPU based,
with an implementation that uses compute shaders for the GPU-side
event functions. The benefit of this solution is that we no longer
need to stall on the CPU when we need to handle GPU-side event
commands.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19313>
2022-10-28 08:35:00 +02:00
Iago Toral Quiroga
8cd50ef071 broadcom/compiler: handle vec2 load/store index
In vulkan, we load descriptors via vulkan resource index, which
returns a vec2, of which we want component 0 which holds the actual
index. Typically, this will be cleaned-up by the time we get to
emitting VIR so the index is a single scalar component, but there
are some cases where this might no be the case, so make sure we don't
assume it to be a scalar, like we do in other places.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19313>
2022-10-28 08:23:32 +02:00
Brian Paul
2ab70c1004 llvmpipe: check rectangle vertices have equal W components
The attribute interpolation code does not handle perspective
correction.  But it's OK if the vertex W components are non-one as
long as they're equal.

This fixes about 30 CTS/dEQP tests.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19331>
2022-10-27 22:05:01 -06:00
Matt Turner
3ef88cd0a2 intel/dev: Set display_ver = 13 on all ADL/RPL/DG2
display_ver doesn't seem to be used anywhere, but if that were to
change, we'd want this to be consistent.

Fixes: c746bf4c5c ("intel/dev: Add display_ver and set adl-p to 13")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19354>
2022-10-28 01:31:44 +00:00
Karol Herbst
dbc4f05ca1 zink: remove leftover work_dim lowering code
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19362>
2022-10-28 01:11:00 +00:00
Karol Herbst
43c5a7a6b4 rusticl/kernel: add work_dim lowering
No driver implements this in hardware, so let's implement it once in the
frontend.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19362>
2022-10-28 01:11:00 +00:00
Karol Herbst
ff24eeee20 rusticl/kernel: lower system values before gathering info
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19362>
2022-10-28 01:11:00 +00:00
Karol Herbst
f54608db6d rusticl/nir: add reads_sysval wrapper
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19362>
2022-10-28 01:11:00 +00:00
Karol Herbst
0961c6aba2 rusticl: add small bitset impl
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19362>
2022-10-28 01:11:00 +00:00
Mike Blumenkrantz
c128cbb5bb zink: always add MUTABLE with EXTENDED_USAGE for image creation
this otherwise makes little sense

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19018>
2022-10-28 00:51:48 +00:00
Mike Blumenkrantz
f2d3826dac zink: don't force attachment usage for images when unsupported
this is illegal even with EXTENDED_USAGE, but it will also probably
explode later when trying to populate the image

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19018>
2022-10-28 00:51:48 +00:00
Mike Blumenkrantz
8de17393f5 zink: fix weird formatting
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19018>
2022-10-28 00:51:48 +00:00
Jesse Natalie
fe73e07a51 d3d12: Set PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19357>
2022-10-27 23:17:47 +00:00
Jesse Natalie
7118b2136e d3d12: Don't multiply cube array sizes by 6
Gallium already does this for us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19357>
2022-10-27 23:17:47 +00:00
Jesse Natalie
e2934435f8 d3d12: Don't put permanently-resident resources in the residency bo list
If the permanently-resident resources are never used, such as a swapchain
buffer in a purely offscreen renderer, it can cause the residency algorithm
to fail, when the permanently-resident resource is least-recently-used,
so we try to wait for it to be idle and evict it, but it never gets evicted.
This triggers an infinite loop.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19357>
2022-10-27 23:17:47 +00:00
Mike Blumenkrantz
82029aed88 zink: rip out unused kernel push constant
this was for supporting clover, but I don't care anymore

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
719ce10b86 zink: add handling for CL-style discrete shader samplers
this splits the bindings for sampler desc sets in CL like
* 32 samplers
* 128 samplerviews
* (compacted only) shader images

and then handles recombination during texop emission

it does NOT change the descriptor limits, which are still clamped to 32

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
1b45e79355 zink: add handling on the vk side for discrete sampler descriptors
just the descriptor layout/set management

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
b900bb2209 zink: always take the compact descriptor size path with kernel shaders
this guarantees compaction of the size arrays

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
efd14b6fc5 zink: emit explicit samplers in ntv based on sampler_mask
not actually used yet

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
6ef8470bb4 zink: add some spirv builder handling for sampled image ops
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
dbf24c6dca zink: simplify image deref handling
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
49a387720e zink: add a nir pass for CL image typing and sampler tracking
cl images and samplers come through untyped, so they need to be typed
before they can be used

samplers are also not combined into the descriptor, so track a mask which
can be used later for emission

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
c67dc62a4c zink: pass image type to image emission
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
b2fcb34e97 zink: rework sampler emission
this simplifies all the different sampler metadata tracking fields to be
more comprehensible

it also increases some array sizes in case future work increases them outside
the compiler areas

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
037bbabcb9 zink: pass KERNEL shaders through successfully
basically just merging with COMPUTE cases

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Mike Blumenkrantz
2a08b97330 zink: match bitsizes in bo rewriting
technically this matters

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
2022-10-27 22:01:34 +00:00
Lionel Landwerlin
e59c4a912b intel/fs: use fs implementation of dump_instructions
This specialized version prints out the liveness count as well as the
maximum liveness count. It was eye opening when seeing the max
liveness jump after lowering of packing instructions which should not
have changed the count.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
2022-10-27 21:05:00 +00:00
Lionel Landwerlin
e5dfff0946 intel/fs: reduce liveness of variables in lowering passes
When lowering a single instruction with a destination VGRF to 2 or
more, the VGRF is now considered partially written by each generated
instruction and that increases its liveness especially in loops. Thus
potentially increasing the number of spills/fills due to register
allocation.

Putting an UNDEF instruction in front of the lowered instructions
allows the IR to limit the liveness of the VGRF, reducing register
pressure.

This has a pretty dramatic effect on spills/fills for RT shaders. Here
the stats on Q2RTX shaders on DG2 (wipping out any spills/fills due to
register allocation) :

Instructions in all programs: 26150 -> 24955 (-4.6%)
SENDs in all programs: 1148 -> 1148 (+0.0%)
Loops in all programs: 4 -> 4 (+0.0%)
Cycles in all programs: 392179 -> 332787 (-15.1%)
Spills in all programs: 132 -> 116 (-12.1%)
Fills in all programs: 262 -> 154 (-41.2%)

Shader-db results on TGL :

total instructions in shared programs: 21158140 -> 21158377 (<.01%)
instructions in affected programs: 76629 -> 76866 (0.31%)
helped: 18
HURT: 20
helped stats (abs) min: 1 max: 60 x̄: 18.89 x̃: 12
helped stats (rel) min: 0.21% max: 3.61% x̄: 1.02% x̃: 0.77%
HURT stats (abs)   min: 1 max: 79 x̄: 28.85 x̃: 18
HURT stats (rel)   min: 0.04% max: 2.81% x̄: 1.13% x̃: 0.79%
95% mean confidence interval for instructions value: -4.82 17.30
95% mean confidence interval for instructions %-change: -0.34% 0.57%
Inconclusive result (value mean confidence interval includes 0).

total loops in shared programs: 5753 -> 5753 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total cycles in shared programs: 798856834 -> 798870688 (<.01%)
cycles in affected programs: 6208395 -> 6222249 (0.22%)
helped: 22
HURT: 17
helped stats (abs) min: 2 max: 8794 x̄: 1438.18 x̃: 782
helped stats (rel) min: 0.05% max: 2.28% x̄: 0.63% x̃: 0.44%
HURT stats (abs)   min: 2 max: 19178 x̄: 2676.12 x̃: 1358
HURT stats (rel)   min: 0.04% max: 23.49% x̄: 2.25% x̃: 0.71%
95% mean confidence interval for cycles value: -952.19 1662.65
95% mean confidence interval for cycles %-change: -0.64% 1.90%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 4078 -> 4066 (-0.29%)
spills in affected programs: 40 -> 28 (-30.00%)
helped: 2
HURT: 0

total fills in shared programs: 2856 -> 2832 (-0.84%)
fills in affected programs: 127 -> 103 (-18.90%)
helped: 2
HURT: 0

total sends in shared programs: 998554 -> 998554 (0.00%)
sends in affected programs: 0 -> 0
helped: 0
HURT: 0

LOST:   0
GAINED: 0

Total CPU time (seconds): 2346.06 -> 2304.80 (-1.76%)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
2022-10-27 21:05:00 +00:00
Lionel Landwerlin
dd6d40429b intel/fs: make split_virtual_grfs deal with partial undefs
v2: fix up UNDEFs instructions (Curro)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
2022-10-27 21:05:00 +00:00
Lionel Landwerlin
14b99df7d9 intel/fs: require UNDEFs register offsets to be aligned to REG_SIZE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
2022-10-27 21:05:00 +00:00
Emma Anholt
59ecbe3fe2 turnip: Fix reservation for indirect compute's IR3_DP_SUBGROUP_ID_SHIFT.
Fixes an assert in GravityMark.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19203>
2022-10-27 20:31:34 +00:00
Alyssa Rosenzweig
78785f3b18 pan/mdg: Don't schedule across memory barrier
Fixes KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-cs

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
2022-10-27 20:13:11 +00:00
Alyssa Rosenzweig
027ee6c9e9 panfrost: Lower MAX_BLOCK_SIZE on Midgard
To match PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, having it be higher in any
dimension is nonsensical and can confuse apps. Fixes tests in
KHR-GLES31.core.texture_buffer.* on Mali-T860.

Fixes: 9b19104a30 ("pan/mdg: Lower PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK on Midgard")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
2022-10-27 20:13:11 +00:00
Alyssa Rosenzweig
934f9bbae7 panfrost: Avoid a XFB special case
This worked around an issue that doesn't apply to the Valhall XFB lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
2022-10-27 20:13:11 +00:00
Alyssa Rosenzweig
0955fe8fe2 panfrost: Use compute-based XFB on Midgard
Now we're back to a single XFB implementation for all gens. Fixes:

   KHR-GLES31.core.draw_indirect.advanced-twoPasses-transformFeedback-arrays
   KHR-GLES31.core.draw_indirect.advanced-twoPasses-transformFeedback-elements

Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
2022-10-27 20:13:11 +00:00
Alyssa Rosenzweig
9e2ce225e6 pan/mdg: Fix 64-bit address arithmetic
Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
2022-10-27 20:13:11 +00:00
Alyssa Rosenzweig
4a626d9829 pan/bi: Clean up sysval handling a bit
Combine some cases.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
2022-10-27 20:13:11 +00:00
Alyssa Rosenzweig
1e208aaef4 panfrost: Don't allow VS side effects on midgard
So we can use the common XFB lowering, and try to reduce the differences between
Midgard and Bifrost (given that Bifrost is conformant and actively maintained,
and Midgard is neither, getting Midgard as close to Bifrost is in the best
interests of Midgard's long term prospects upstream). Piles of KHR-GLES31 tests
from Fail -> Skip.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
2022-10-27 20:13:11 +00:00
Alyssa Rosenzweig
1bb68d9532 panfrost: Zero polygon list for fragment-only
Even with hierarchical tiling. Otherwise if there's garbage leftover (due to BO
caching), a fragment-only batch can raise DATA_INVALID_FAULT. Fixes many tests
in KHR-GLES31.core.compute_shader.* on Mali-T860, including

   KHR-GLES31.core.compute_shader.build-separable

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
2022-10-27 20:13:11 +00:00
Alyssa Rosenzweig
63320c691a nir/lower_idiv: Inline convert_instr_precise
Now that we only have one convert_instr path, this is simpler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19303>
2022-10-27 19:37:14 +00:00