Commit graph

34484 commits

Author SHA1 Message Date
Marc-André Lureau
17b27725fe drisw: use getImageShm() if available
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
2018-05-30 09:11:54 +10:00
Marc-André Lureau
9feaf33371 drisw: learn to query shmid handle type
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
2018-05-30 09:11:54 +10:00
Marc-André Lureau
cf54bd5e83 drisw: use shared memory when possible
If drisw_loader_funcs implements put_image_shm, allocates display
target data with shared memory and display with put_image_shm().

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
2018-05-30 09:11:54 +10:00
Marc-André Lureau
63c427fa71 drisw: use putImageShm if available
If the DRIswrastLoaderExtension implements putImageShm, bind it to
drisw_loader_funcs.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
2018-05-30 09:11:53 +10:00
Dave Airlie
b7ac0779e0 gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*
This just renames this as we want to add an shm handle which
isn't really drm related.

Originally by: Marc-André Lureau <marcandre.lureau@gmail.com>
(airlied: I used this sed script instead)
This was generated with:
 git grep -l 'DRM_API_' | xargs sed -i 's/DRM_API_/WINSYS_/g'

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-05-30 09:11:53 +10:00
Marc-André Lureau
d2eaff33d0 gallium: move winsys handle to it's own file.
This will be used in the drisw interface later, which isn't
drm specific.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-05-30 09:11:53 +10:00
Jan Vesely
41b878e1bd clover: Cleanup compat code for llvm < 3.9
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-By: Aaron Watry <awatry@gmail.com>
2018-05-29 17:36:16 -04:00
Jan Vesely
d424be0fed clover: Fix build after llvm r332881.
v2: fix whitespace and indentation

r332881 added an extra parameter to the emit function.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106619
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-By: Aaron Watry <awatry@gmail.com>
Tested-By: Aaron Watry <awatry@gmail.com>
Tested-by: Kai Wasserbäch <kai@dev.carbon-project.org>
2018-05-29 17:36:16 -04:00
Thierry Reding
9e539012df tegra: Treat resources with modifiers as scanout
Resources created with modifiers are treated as scanout because there is
no way for applications to specify the usage (though that capability may
be useful to have in the future). Currently all the resources created by
applications with modifiers are for scanout, so make sure they have bind
flags set accordingly.

This is necessary in order to properly export buffers for such resources
so that they can be shared with scanout hardware.

Tested-by: Daniel Kolesa <daniel@octaforge.org>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-29 16:48:37 +02:00
Thierry Reding
9603d81df0 tegra: Fix scanout resources without modifiers
Resources created for scanout but without modifiers need to be treated
as pitch-linear. This is because applications that don't use modifiers
to create resources must be assumed to not understand modifiers and in
turn won't be able to create a DRM framebuffer and passing along which
modifiers were picked by the implementation.

Tested-by: Daniel Kolesa <daniel@octaforge.org>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-29 16:48:34 +02:00
Thierry Reding
bd3e97e5aa tegra: Remove usage of non-stable UAPI
This code path is no longer required with framebuffer modifier support.

Tested-by: Daniel Kolesa <daniel@octaforge.org>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-29 16:47:45 +02:00
Pierre Moreau
f0e80e123c nv50/ir: Extend ImmediateValue::applyLog2 to 64-bit integers
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-05-29 13:37:45 +02:00
Pierre Moreau
03f592a164 util/u_math: Implement a logbase2 function for unsigned long
v2 (Karol Herbst <kherbst@redhat.com>):
* removed unneeded ll
* ll -> ull

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-05-29 13:37:45 +02:00
Rhys Perry
57e721a456 gm107/ir: prevent WaW hazards in instruction scheduling
Previously, findFirstUse() only considered reads "uses". This fixes that
by making it check both an instruction's sources and definitions. It
also shortens both findFistUse() and findFirstDef() along the way.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-05-28 13:59:56 -04:00
Gert Wollny
1aec4a07d4 r600: Fix SSG when not all components are written
Make sure only those components are written to that are specified in the
write mask.

Fixes:
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_float_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_float_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_float_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_float_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_float_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_float_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_vec3_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_vec3_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_vec3_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_vec3_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_vec3_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_vec3_fragment
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-05-28 02:57:46 +01:00
Gert Wollny
42cd2810aa r600: Correct IDIV if DST and SRC use the same temporary
In cases like

  IDIV TEMP[0].xy TEMP[0].xx TEMP[1].yy

the result will be written to the same register that is also a source register.
Since the components are evaluated one by one, this may result in overwriting
the source value for a later operation. Work around this by adding another
temporary to store the result if the destination temporary index is equal to
one of the source temporary indices.

Fixes:
  dEQP-GLES2.functional.shaders.operator.binary_operator.div.*
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-05-28 02:57:46 +01:00
Marek Olšák
18c50498db radeonsi: remove unused variable addr_vec
trivial
2018-05-25 18:37:57 -04:00
Marek Olšák
2f65c67043 radeonsi: fix passing gl_ClipVertex for GS and tess
Also add the fprintf call.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-25 16:46:00 -04:00
Marek Olšák
a7d61c0753 radeonsi: fix color inputs/outputs for GS and tess
GS is tested, tessellation is untested.

Have outputs_written_before_ps for HW VS and outputs_written for other
stages. The reason is that COLOR and BCOLOR alias for HW VS, which
drives elimination of VS outputs based on PS inputs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-25 16:46:00 -04:00
Marek Olšák
92ea9329e5 radeonsi: fix incorrect parentheses around VS-PS varying elimination
I don't know if it caused issues.

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-25 16:46:00 -04:00
Alok Hota
fb20ae0374 swr/rast: Adjusted avx512 primitive assembly for msvc codegen
Optimize AVX-512 PA Assemble (PA_STATE_OPT). Reduced generated code by
about 4x, MSVC compiler was going crazy making temporaries and
split-loading inputs onto the stack unless explicit AVX-512 load ops
were added

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-05-25 10:57:02 -05:00
Alok Hota
b3360f5c8b swr/rast: Moved memory init out of core swr init
Added two new files for a wrapper function for initialization

v2: added missing include for single architecture builds

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-05-25 10:56:55 -05:00
Alok Hota
b6b114c1ae swr/rast: Removed superfluous JitManager argument from passes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-05-25 10:56:49 -05:00
Alok Hota
98d0201577 swr/rast: Renamed MetaData calls
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-05-25 10:56:43 -05:00
Alok Hota
14b5cac0be swr/rast: Use metadata to communicate between passes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-05-25 10:56:37 -05:00
Alok Hota
f09636e2e1 swr/rast: Check gCoreBuckets/CORE_BUCKETS equal length at compile time
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-05-25 10:56:01 -05:00
Alok Hota
cfe75cc7b5 swr/rast: Added in-place building to SCATTERPS
SCATTERPS previously assumed it was being used with an existing basic
block

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-05-25 10:55:37 -05:00
Marek Olšák
508b423dd6 radeonsi: set DB_EQAA.MAX_ANCHOR_SAMPLES correctly
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-24 13:41:57 -04:00
Marek Olšák
07e02c8617 radeonsi: round ps_iter_samples in set_min_samples
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-24 13:41:57 -04:00
Marek Olšák
510c88f9d1 radeonsi: remove redundant ps_iter_samples clamp
si_get_ps_iter_samples already does this.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-24 13:41:56 -04:00
Marek Olšák
b936f9aa32 radeonsi: disable primitive binning for all blitter ops
same as amdvlk.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-24 13:41:56 -04:00
Dave Airlie
f2f464de57 tgsi/scan: add hw atomic to the list of memory accessing files
This fixes 4 out of 5 cases in:
arb_framebuffer_no_attachments-atomic on cayman.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org>
2018-05-23 03:51:40 +01:00
Roland Scheidegger
7b89fcec41 llvmpipe: improve rasterization discard logic
This unifies the explicit rasterization discard as well as the implicit
rasterization disabled logic (which we need for another state tracker),
which really should do the exact same thing.
We'll now toss out the prims early on in setup with (implicit or
explicit) discard, rather than do setup and binning with them, which
was entirely pointless.
(We should eventually get rid of implicit discard, which should also
enable us to discard stuff already in draw, hence draw would be
able to skip the pointless clip and fallback stages in this case.)
We still need separate logic for only null ps - this is not the same
as rasterization discard. But simplify the logic there and don't count
primitives simply when there's an empty fs, regardless of depth/stencil
tests, which seems perfectly acceptable by d3d10.
While here, also fix statistics for primitives if face culling is
enabled.
No piglit changes.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2018-05-23 04:23:32 +02:00
Vinson Lee
85f61197df v3d: Include v3d_drm.h path.
Fix build error.

  CC       v3d_blit.lo
In file included from v3d_blit.c:27:0:
v3d_context.h:39:10: fatal error: v3d_drm.h: No such file or directory
 #include "v3d_drm.h"
          ^~~~~~~~~~~

Fixes: 8a793d42f1 ("v3d: Switch the vc5 driver to using the finalized V3D UABI.")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-05-21 11:15:47 -07:00
Dave Airlie
bfa74bb44d virgl: set texture buffer offset alignment to disable ARB_texture_buffer_range.
The host side hasn't got support for this feature yet, so don't enable it
unless we get the caps from the host.

This makes the texture buffer range piglit tests skip now.

Fixes: fe0647df5a (virgl: add offset alignment values to to v2 caps struct)
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-05-21 12:44:55 +10:00
Aaron Watry
cfe582f9dc r600/compute: Mark several functions as static
They're not used anywhere else, so keep them private

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
2018-05-19 10:22:16 -05:00
Aaron Watry
d21e64c626 r600/compute: Remove unused compute_memory_pool functions
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
2018-05-19 10:21:57 -05:00
Roland Scheidegger
6f558fb0f7 draw: get rid of special logic to not emit null tris
I've confirmed after 77554d220d we no
longer need this to pass some tests from another api (as we no longer
generate the bogus extra null tris in the first place).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2018-05-19 02:49:58 +02:00
Marek Olšák
3d64ed5785 radeonsi: skip ES output stores for undefined output components
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-05-18 13:38:07 -04:00
Brian Paul
42aee8f4f6 llvmpipe: fix check for a no-op shader
The tgsi_info.num_tokens fix broke llvmpipe's detection of no-op shaders.
Fix the code to check for num_instructions <= 1 instead.

Fixes: 8fde9429c3 ("tgsi: fix incorrect tgsi_shader_info::num_tokens
computation")
Tested-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-05-18 09:09:41 -06:00
Brian Paul
8fde9429c3 tgsi: fix incorrect tgsi_shader_info::num_tokens computation
We were incrementing num_tokens in each loop iteration while parsing
the shader.  But each call to tgsi_parse_token() can consume more than
one token (and often does).  Instead, just call the tgsi_num_tokens()
function.

Luckily, this issue doesn't seem to effect any current users of this
field (llvmpipe just checks for <= 1, for example).

Reviewed-by: Neha Bhende<bhenden@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-05-17 15:02:05 -06:00
Marek Olšák
f9eb1ef870 amd: remove support for LLVM 4.0
It doesn't support GFX9.

Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-05-17 14:54:41 -04:00
Alok Hota
936ce75285 swr/rast: Added FEClipRectangles event
and also added some comments

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
2018-05-17 10:53:14 -05:00
Alok Hota
a33d376133 swr/rast: Whitespace and tab-to-spaces changes
Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
2018-05-17 10:53:10 -05:00
Alok Hota
7970fcff25 swr/rast: fix VCVTPD2PS generation for AVX512
Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
2018-05-17 10:53:06 -05:00
Alok Hota
a0dddac1cb swr/rast: Rectlist support for GS
Add rectlist as an option for GS.  Needed to support some driver
optimizations.

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
2018-05-17 10:53:01 -05:00
Alok Hota
7926d18fa5 swr/rast: Remove unneeded virtual from methods
Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
2018-05-17 10:52:21 -05:00
Stefan Schake
b0acc3a562 broadcom/vc4: Native fence fd support
With the syncobj support in place, lets use it to implement the
EGL_ANDROID_native_fence_sync extension. This mostly follows previous
implementations in freedreno and etnaviv.

v2: Drop the flags (Eric)
    Handle in_fence_fd already in job_submit (Eric)
    Drop extra vc4_fence_context_init (Eric)
    Dup fds with CLOEXEC (Eric)
    Mention exact extension name (Eric)

Signed-off-by: Stefan Schake <stschake@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-05-17 16:04:30 +01:00
Stefan Schake
44036c354d broadcom/vc4: Store job fence in syncobj
This gives us access to the fence created for the render job.

v2: Drop flag (Eric)

Signed-off-by: Stefan Schake <stschake@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-05-17 16:04:28 +01:00
Stefan Schake
9ed05e2520 broadcom/vc4: Detect syncobj support
We need to know if the kernel supports syncobj submission since otherwise
all the DRM syncobj calls fail.

v2: Use drmGetCap to detect syncobj support (Eric)

Signed-off-by: Stefan Schake <stschake@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-05-17 16:04:26 +01:00