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Author SHA1 Message Date
Rohan Garg
e103afe7be brw: run the nir_opt_offsets pass and set the maximum offset size
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Perf A/B testing on DG2: no changes
Perf A/B testing on BMG: +2.1% Blackops3, +1.5% Cyberpunk

DG2 stats (mostly insignificant):
Assassins Creed Valhalla:
 Totals from 1169 (55.67% of 2100) affected shaders:
 Instrs: 509237 -> 509215 (-0.00%)
 Cycle count: 30614325 -> 30607419 (-0.02%); split: -0.03%, +0.00%
 Non SSA regs after NIR: 83434 -> 85909 (+2.97%)

Blackops 3:
 Totals from 1045 (64.63% of 1617) affected shaders:
 Instrs: 527312 -> 527310 (-0.00%)
 Cycle count: 496912222 -> 496902846 (-0.00%); split: -0.00%, +0.00%
 Non SSA regs after NIR: 106883 -> 109095 (+2.07%)

Cyberpunk:
 Totals from 706 (56.03% of 1260) affected shaders:
 Instrs: 345976 -> 345974 (-0.00%); split: -0.00%, +0.00%
 Cycle count: 9775138 -> 9775472 (+0.00%); split: -0.00%, +0.00%
 Max live registers: 40295 -> 40297 (+0.00%)
 Non SSA regs after NIR: 93245 -> 94718 (+1.58%)

Fortnite:
 Totals from 4210 (55.98% of 7521) affected shaders:
 Instrs: 2205471 -> 2205469 (-0.00%)
 Cycle count: 91451040 -> 91450956 (-0.00%); split: -0.00%, +0.00%
 Non SSA regs after NIR: 952354 -> 961664 (+0.98%)

LNL stats (notable changes):
Assassins Creed Valhalla:
 Totals from 1684 (83.57% of 2015) affected shaders:
 Instrs: 774305 -> 764501 (-1.27%); split: -1.27%, +0.01%
 Cycle count: 58845842 -> 58699250 (-0.25%); split: -0.98%, +0.73%
 Spill count: 625 -> 638 (+2.08%)
 Fill count: 1490 -> 1503 (+0.87%)
 Scratch Memory Size: 41984 -> 44032 (+4.88%)
 Max live registers: 196424 -> 197561 (+0.58%); split: -0.10%, +0.68%

Blackops 3:
 Totals from 1125 (76.53% of 1470) affected shaders:
 Instrs: 781749 -> 773275 (-1.08%); split: -1.08%, +0.00%
 Subgroup size: 22896 -> 22912 (+0.07%)
 Cycle count: 659864454 -> 654641032 (-0.79%); split: -1.10%, +0.31%
 Max live registers: 116772 -> 116854 (+0.07%); split: -0.01%, +0.08%
 Non SSA regs after NIR: 172648 -> 168260 (-2.54%); split: -2.55%, +0.01%

Control:
 Totals from 378 (51.50% of 734) affected shaders:
 Instrs: 148184 -> 147544 (-0.43%)
 Cycle count: 6905200 -> 6913366 (+0.12%); split: -0.30%, +0.42%
 Max live registers: 41271 -> 41281 (+0.02%)
 Non SSA regs after NIR: 44964 -> 43868 (-2.44%); split: -2.45%, +0.01%

Cyberpunk:
 Totals from 1141 (92.46% of 1234) affected shaders:
 Instrs: 636744 -> 629333 (-1.16%)
 Subgroup size: 24256 -> 24272 (+0.07%)
 Cycle count: 24952258 -> 24801298 (-0.60%); split: -1.39%, +0.78%
 Max live registers: 125848 -> 126855 (+0.80%); split: -0.00%, +0.80%
 Non SSA regs after NIR: 127399 -> 119837 (-5.94%); split: -5.95%, +0.02%

Fortnite:
 Totals from 5497 (83.52% of 6582) affected shaders:
 Instrs: 4072831 -> 4041852 (-0.76%); split: -0.77%, +0.01%
 Subgroup size: 103296 -> 103312 (+0.02%)
 Cycle count: 133046874 -> 132789242 (-0.19%); split: -0.67%, +0.48%
 Spill count: 7218 -> 7254 (+0.50%); split: -0.33%, +0.83%
 Fill count: 11724 -> 11749 (+0.21%); split: -0.34%, +0.55%
 Scratch Memory Size: 591872 -> 599040 (+1.21%)
 Max live registers: 816530 -> 818522 (+0.24%); split: -0.01%, +0.26%
 Non SSA regs after NIR: 1610296 -> 1560284 (-3.11%); split: -3.11%, +0.00%

Hitman3:
 Totals from 4713 (92.39% of 5101) affected shaders:
 Instrs: 2731598 -> 2698224 (-1.22%)
 Cycle count: 186422098 -> 185472640 (-0.51%); split: -1.12%, +0.61%
 Spill count: 3244 -> 3242 (-0.06%)
 Fill count: 9937 -> 9933 (-0.04%)
 Max live registers: 585035 -> 589801 (+0.81%); split: -0.00%, +0.82%
 Non SSA regs after NIR: 347681 -> 324314 (-6.72%); split: -6.73%, +0.01%

Hogwarts Legacy:
 Totals from 930 (59.81% of 1555) affected shaders:
 Instrs: 464146 -> 459526 (-1.00%); split: -1.00%, +0.01%
 Subgroup size: 19104 -> 19120 (+0.08%)
 Cycle count: 24062460 -> 24078964 (+0.07%); split: -0.49%, +0.56%
 Spill count: 2068 -> 1964 (-5.03%); split: -5.22%, +0.19%
 Fill count: 2342 -> 2205 (-5.85%); split: -6.40%, +0.56%
 Scratch Memory Size: 147456 -> 141312 (-4.17%)
 Max live registers: 112384 -> 112787 (+0.36%); split: -0.08%, +0.44%
 Non SSA regs after NIR: 80293 -> 79161 (-1.41%); split: -1.72%, +0.32%

Metro Exodus:
 Totals from 29755 (78.62% of 37846) affected shaders:
 Instrs: 11495578 -> 11492951 (-0.02%); split: -0.02%, +0.00%
 Subgroup size: 644688 -> 644704 (+0.00%)
 Cycle count: 301572068 -> 301548054 (-0.01%); split: -0.03%, +0.02%
 Max live registers: 3369504 -> 3370454 (+0.03%); split: -0.00%, +0.03%
 Non SSA regs after NIR: 2476561 -> 2396090 (-3.25%); split: -3.27%, +0.02%

Red Dead Redemption 2:
 Totals from 4161 (78.61% of 5293) affected shaders:
 Instrs: 2428782 -> 2409032 (-0.81%); split: -0.82%, +0.00%
 Subgroup size: 85344 -> 85360 (+0.02%)
 Cycle count: 8514984142 -> 8533415324 (+0.22%); split: -0.02%, +0.23%
 Spill count: 4659 -> 4674 (+0.32%); split: -0.02%, +0.34%
 Fill count: 11236 -> 11231 (-0.04%); split: -0.19%, +0.14%
 Scratch Memory Size: 398336 -> 397312 (-0.26%)
 Max live registers: 473946 -> 475798 (+0.39%); split: -0.08%, +0.47%
 Non SSA regs after NIR: 616820 -> 567706 (-7.96%); split: -8.09%, +0.12%

Rise Of The Tomb Raider:
 Totals from 68 (46.58% of 146) affected shaders:
 Instrs: 28209 -> 27801 (-1.45%)
 Subgroup size: 1584 -> 1600 (+1.01%)
 Cycle count: 16182992 -> 16249364 (+0.41%); split: -0.97%, +1.38%
 Max live registers: 7320 -> 7296 (-0.33%); split: -0.38%, +0.05%
 Non SSA regs after NIR: 8438 -> 8207 (-2.74%); split: -2.82%, +0.08%

Spiderman Remastered:
 Totals from 6403 (93.87% of 6821) affected shaders:
 Instrs: 5662713 -> 5597949 (-1.14%); split: -1.28%, +0.14%
 Cycle count: 282861519016 -> 279806958122 (-1.08%); split: -1.26%, +0.18%
 Spill count: 61150 -> 60754 (-0.65%); split: -1.13%, +0.48%
 Fill count: 162597 -> 163190 (+0.36%); split: -0.84%, +1.21%
 Scratch Memory Size: 5834752 -> 5804032 (-0.53%); split: -0.70%, +0.18%
 Max live registers: 901926 -> 903820 (+0.21%); split: -0.01%, +0.22%
 Non SSA regs after NIR: 555053 -> 521016 (-6.13%); split: -6.14%, +0.01%

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:24 +00:00
Rohan Garg
8a5e062e5e brw: store the buffer offset for load/store intrinsics 
This will later be encoded by the backend into the
LSC extended descriptor message.

Reworks:
  * Sagar: Add nir_intrinsic_ssbo_atomic_swap

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:24 +00:00
Rohan Garg
0186113640 brw: encode the offset into the message descriptor for Xe2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:24 +00:00
Rohan Garg
937d37f0b1 brw: introduce MEMORY_LOGICAL_ADDRESS_OFFSET to encode address offsets 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:24 +00:00
Lionel Landwerlin
d5a58364b1 brw: add new helper for immediate integer register with type 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:24 +00:00
Lionel Landwerlin
50dab62f57 nir/opt_offsets: add support for intel intrinsics 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:23 +00:00
Lionel Landwerlin
16fca611d7 nir: add new intel ssbo intrinsics 
Similar to ir3 ones, to optimize offsets in the backend.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:23 +00:00
Lionel Landwerlin
ba119c73c6 intel: replace RANGE_BASE by BASE for uniform block loads 
We're not currently using RANGE_BASE and we'll use BASE for offset
optimizations on Xe2+.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:23 +00:00
Rohan Garg
909ec6ff1f nir/lower_io: add io_offset support for more intrinsics 
This will be used by upcoming changes in the intel compiler.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:22 +00:00
Lionel Landwerlin
098249ba66 brw: print descriptor & extended descriptors 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:22 +00:00
Lionel Landwerlin
8ea124f877 nir/divergence: add missing intel intrinsics 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:21 +00:00
Lionel Landwerlin
87ef9aabe9 intel: fix monitor build dependencies 
Signed-off-by: Lionel Landwerlin <llandwerlin@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
 2025-06-22 10:55:21 +00:00
Doug Nazar
c3980bb4ec glx: Fix memory leak with software dri
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dri_screen_init() now calls glx_screen_init() directly. Calling
twice overwrites the config.

Fixes: 7930fe5f01 ("glx: unify dri screen init")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35525>
 2025-06-21 23:47:13 +00:00
Lucas Stach
3387e9e8e9 Revert "etnaviv/ci: document new failure"
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This reverts commit 757ad6a333. This test has been flagged as failing
due to something that looks more like a runner issue than a real test
failure and it has been showing up as unexpected pass in later CI runs.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35671>
 2025-06-21 18:59:24 +00:00
Christian Gmeiner
74526442b2 etnaviv: nir: Use nir offset lowering
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We can use the offset lowering for
 - nir_texop_tex in vertex shader only
 - nir_texop_txf

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35573>
 2025-06-21 17:09:17 +00:00
Lucas Stach
3a40d5a7bf etnaviv: don't advertise anisotropic filtering on GPUs with NO_ANISTRO_FILTER
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Anisotropic filtering is generally supported starting with halti0, but there
is a separate feature bit telling us that the filter is not available.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35666>
 2025-06-21 11:59:29 +00:00
Lucas Stach
4b424e9b86 etnaviv: use TX_SEAMLESS_CUBE to determine seamless cubemap support 
I have no idea why the HWDB includes two distinct bits that seem to
relate to seamless cubemap support. However, the only cores where
both bits disagree are NPUs (which don't have any samplers) and the
GC880, which is currently special cased in the driver.

Use TX_SEAMLESS_CUBE to determine seamless cubemap support, which
seems to accurately reflect the real support status.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35666>
 2025-06-21 11:59:29 +00:00
Eric Engestrom
d31b0c9b3b egl/meson: include glvnd in the devenv
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This was working by accident in the case where `-D glvnd-vendor-name`
was not set, because `meson devenv` adds all the folders that produce
a lib to `LD_LIBRARY_PATH` and the system's glvnd's json was pointing
to the same filename as the build had, which ended up getting picked up.

This breaks when `-D glvnd-vendor-name` is set to any other value than
the one set by the distro packagers though, so let's set it up properly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35652>
 2025-06-20 22:18:22 +00:00
Eric Engestrom
367fb5e233 egl/meson: allow passing a full path to the glvnd json file 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35652>
 2025-06-20 22:18:22 +00:00
Eric Engestrom
b952c1a26a egl/meson: move glvnd config file after libEGL 
Necessary for the next commit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35652>
 2025-06-20 22:18:21 +00:00
Eric Engestrom
2e8d14406f egl/meson: reuse existing glvnd_vendor_name variable 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35652>
 2025-06-20 22:18:21 +00:00
Eric Engestrom
b5b49dcfd7 egl/meson: simplify glvnd json configuration 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35652>
 2025-06-20 22:18:20 +00:00
Eric Engestrom
413dbcdf79 meson: include VkLayer_MESA_overlay in the devenv
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See https://github.com/KhronosGroup/Vulkan-Loader/blob/main/docs/LoaderLayerInterface.md#linux-layer-discovery

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35650>
 2025-06-20 21:51:17 +00:00
Eric Engestrom
294d8ce80a meson: include VkLayer_MESA_device_select in the devenv 
See https://github.com/KhronosGroup/Vulkan-Loader/blob/main/docs/LoaderLayerInterface.md#linux-layer-discovery

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35650>
 2025-06-20 21:51:17 +00:00
Eric Engestrom
6b11a53a3a meson: include VkLayer_INTEL_nullhw in the devenv 
See https://github.com/KhronosGroup/Vulkan-Loader/blob/main/docs/LoaderLayerInterface.md#linux-layer-discovery

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35650>
 2025-06-20 21:51:17 +00:00
Alyssa Rosenzweig
43a47266c8 hk: merge adjacent CDM control streams 
this reduces submission overhead in the kernel/firmware.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35662>
 2025-06-20 21:38:12 +00:00
Alyssa Rosenzweig
f7db4afd09 hk: use fast-clears for empty render passes 
this generalizes our trivial VDM optimization.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35662>
 2025-06-20 21:38:12 +00:00
Alyssa Rosenzweig
9cdf486f14 hk: implement vkCmdClear*Image with fast-clears 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35662>
 2025-06-20 21:38:11 +00:00
Alyssa Rosenzweig
7120f86035 libagx: add fast-clear kernels 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35662>
 2025-06-20 21:38:11 +00:00
Alyssa Rosenzweig
908d12d346 libagx: export coordinate twiddle routine 
we'll use for both image atomics and fast-clears

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35662>
 2025-06-20 21:38:11 +00:00
Alyssa Rosenzweig
319a6259d9 libagx: add agx_2d grid helper 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35662>
 2025-06-20 21:38:11 +00:00
Alyssa Rosenzweig
349e802e78 ail,asahi,hk: distinguish logical vs allocation compression 
the hw uses the wrong definition of compressability of mip levels in some
places, but not in others. we need to distinguish these for correct fast clears.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35662>
 2025-06-20 21:38:11 +00:00
Alyssa Rosenzweig
9740474021 ail: generalize solid mode values 
this is blocksize dependenant, fill in the gaps.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35662>
 2025-06-20 21:38:11 +00:00
Alyssa Rosenzweig
cdb4463b52 asahi,hk: fix ts allocation for more shader types 
3c5c3d7819 ("hk: fix texture state count"), part 2.

Backport-to: 25.1
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35662>
 2025-06-20 21:38:10 +00:00
Marek Olšák
d4b742f934 radeonsi: fix printing asm for the first shader of merged shaders for ACO 
When we print asm for merged VS+TCS, we need to record asm for VS
even when only TCS is being printed because they are printed together.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35620>
 2025-06-20 21:21:27 +00:00
Marek Olšák
23c3646164 radeonsi: fix tess regression with latest LLVM git 
The problem was that SGPRs returned from LS were treated as VGPRs by LLVM
because LS executes conditionally. The workaround is to use input SGPRs
initialized by the hw (i.e. parameters of the wrapper function) instead of
the ones returned by LS.

Fixes: 80236f2367 - ac/nir/tess: add if/endif for HS threads in NIR instead of ACO/LLVM

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35620>
 2025-06-20 21:21:27 +00:00
Eric Engestrom
b3ed7f7b63 radeonsi/ci: reduce coverage of radeonsi-vangogh-glcts 
It currently takes 15min of test run time, which is higher than what
a merge-pipeline test is allowed.

Reduce it to 10min, and reduce the timeouts which were way too high.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35588>
 2025-06-20 20:24:59 +00:00
Eric Engestrom
fb8c2a6318 turnip/ci: document vkd3d regression 
It started failing after a commit in the 2782fa2c...df55ea8c range.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35661>
 2025-06-20 20:08:57 +00:00
Emma Anholt
e9d75ce16b ci/tu: Sync up a660's flakes with a618 where they seem to match up.
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
and generalize a couple more things into regexes.  I noticed these after
enabling 660 flake reporting and starting to see them roll in on the CI
channel.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35659>
 2025-06-20 19:46:45 +00:00
Emma Anholt
8e22420187 ci/tu: Don't forget to report flakes on a660, too. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35659>
 2025-06-20 19:46:45 +00:00
Emma Anholt
2919d64d98 ci/tu: Add some recent flakes and consolidate lists into regexes. 
I was going to stability test an MR, and for that I want the flakes list
to be truthful.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35659>
 2025-06-20 19:46:45 +00:00
Eric Engestrom
6addaca3d4 hasvk: only run tests on x86 (32 & 64 bit) 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13305
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35635>
 2025-06-20 19:32:18 +00:00
Danylo Piliaiev
9db945c3be tu: Add info about usage to command buffers tracepoint 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35637>
 2025-06-20 19:15:44 +00:00
Danylo Piliaiev
9f74fcffe4 tu: Add MESA_TRACE_FUNC to submit and BO alloc paths 
Makes much easier to see how slow are submits and BO allocs,
which sometimes happen together.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35637>
 2025-06-20 19:15:44 +00:00
Danylo Piliaiev
6e5944ec4b tu: Cache copy timestamp cs to avoid allocations on submit 
For non-ONE_TIME_SUBMIT command buffers we have to create CS that
copies u_trace timestamps. Having cs pool allows us to avoid
allocations in most cases.

Together with previous commit, BO allocations on submit would be
rare during normal u_trace tracing.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35637>
 2025-06-20 19:15:44 +00:00
Danylo Piliaiev
a1b9aa3385 tu: Suballocate u_trace buffers to avoid allocations on submit 
For non-ONE_TIME_SUBMIT command buffers we have to copy tracepoints
which leads to BO allocations. That adds overhead we don't want,
especially when there are many tiny submissions.

While suballocator for u_trace BOs is allocated only when needed,
it's not deallocated afterwards, since the point where it's not needed
is tricky to determine.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35637>
 2025-06-20 19:15:44 +00:00
Alyssa Rosenzweig
8ec4337c1f hk: drop psiz writes with !largePoints 
affects geom/tess mostly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35658>
 2025-06-20 18:46:16 +00:00
Alyssa Rosenzweig
691aa581c3 hk: optimize !largePoints 
should slightly help proton

requires reordering the uvs lowering to be after tes lowering since that can
insert psiz writes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35658>
 2025-06-20 18:46:16 +00:00
Alyssa Rosenzweig
9d7301b2d1 hk: disable custom border for proton 
zoom.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35658>
 2025-06-20 18:46:16 +00:00
Alyssa Rosenzweig
ba4bab0584 hk: make border colour lint quieter 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35658>
 2025-06-20 18:46:16 +00:00