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Author SHA1 Message Date
Daniel Schürmann
dfc13fcf9f aco: introduce Operand flag 'CopyKill' 
This flag indicates that the Operand must be copied in order to satisfy register
constraints. The copy is immediately killed by the instruction.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30299>
 2024-09-10 09:44:53 +00:00
Daniel Schürmann
91f65d5935 aco/live_var_analysis: use Clobbered flag to calculate additional operand demand 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30299>
 2024-09-10 09:44:53 +00:00
Daniel Schürmann
5a6fa8a8eb aco: introduce new Operand flag 'Clobbered' 
This flag indicates that the Operand's register gets clobbered by the instruction.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30299>
 2024-09-10 09:44:53 +00:00
Daniel Schürmann
1c14013b9e aco/live_var_analysis: Don't attempt to re-insert the same temporary twice into live set 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30299>
 2024-09-10 09:44:53 +00:00
Samuel Pitoiset
e621f0c173 radv: rework emitting indirect compute pipelines with DGC 
Instead of recreating the packets in the DGC prepare shader, the best
solution is to emit them to a temporary CS object at pipeline creation
time. Then in the DGC prepare shader, the driver just needs to copy
the packets.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31101>
 2024-09-10 09:13:44 +00:00
Samuel Pitoiset
8802612458 radv: advertise VK_KHR_pipeline_binary 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
 2024-09-10 08:19:52 +00:00
Samuel Pitoiset
b4d6d88c6b radv: add support for importing pipeline binaries 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
 2024-09-10 08:19:52 +00:00
Samuel Pitoiset
96a300a3f0 radv: add support for capturing pipeline binaries 
When VK_PIPELINE_CREATE_2_CAPTURE_DATA_BIT_KHR is set, implementations
shouldn't store pipeline data to an internal cache.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
 2024-09-10 08:19:52 +00:00
Samuel Pitoiset
be06bfcbed radv: add initial support for pipeline binaries 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
 2024-09-10 08:19:52 +00:00
Samuel Pitoiset
32a4c9e117 radv: disable the in-memory cache when disableInternalCache is true 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
 2024-09-10 08:19:52 +00:00
Samuel Pitoiset
af76f48fc2 radv: make pipeline hashing functions non-static 
They will be used to generate pipeline hashes from pCreateInfo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
 2024-09-10 08:19:52 +00:00
Samuel Pitoiset
3423facbd1 radv: store whether a RT pipeline is a library to the shaders cache 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
 2024-09-10 08:19:52 +00:00
Samuel Pitoiset
0a15dcf95c radv: store the number of RT stages per pipeline to the shaders cache 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
 2024-09-10 08:19:52 +00:00
Samuel Pitoiset
42b1c728b2 radv: store the SHA1 RT stage to the shaders cache 
When pipeline binaries are imported, that SHA1 would also need to be
imported in order to deduplicate shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
 2024-09-10 08:19:52 +00:00
Samuel Pitoiset
3d2cd4687c radv: rework helpers for serialize/deserialize shaders 
They will be used to serialize/deserialize shaders for pipeline
binaries.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
 2024-09-10 08:19:52 +00:00
Samuel Pitoiset
0c7896deef Revert "radv: specialize push constant stages with DGC" 
This change was wrong but there is nothing testing this. For example,
if we have a pipeline with VS+GS+FS and DGC only updates push constants
for VS. On GFX9+, VS is merged to GS, so the VS push constants info
would be zero and nothing would be emitted.

This reverts commit 45319cb253.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31099>
 2024-09-10 07:39:54 +00:00
Dave Airlie
7531f6fd9c radv/anv/video: handling encoding both sps and pps in same buffer 
This API should allow encoding these back to back into the same
buffer, so handle it properly.

Cc: mesa-stable
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31086>
 2024-09-10 06:03:15 +00:00
Georg Lehmann
8a43b1e7da aco/ra: do not reuse killed vcc 
VCC should only be used if nessecary, to keep it free for instructions
that need/prefer it.

Foz-DB Navi31:
Totals from 132 (0.17% of 79395) affected shaders:
Instrs: 832538 -> 832608 (+0.01%); split: -0.03%, +0.04%
CodeSize: 4310888 -> 4301792 (-0.21%); split: -0.22%, +0.01%
Latency: 6238465 -> 6239198 (+0.01%); split: -0.04%, +0.05%
InvThroughput: 5332353 -> 5336363 (+0.08%); split: -0.03%, +0.10%
Copies: 59420 -> 59392 (-0.05%); split: -0.11%, +0.06%
VALU: 459318 -> 459187 (-0.03%); split: -0.03%, +0.00%
SALU: 109208 -> 109081 (-0.12%); split: -0.14%, +0.03%
VOPD: 6426 -> 6557 (+2.04%); split: +2.10%, -0.06%

Foz-DB Navi21:
Totals from 386 (0.49% of 79395) affected shaders:
Instrs: 3254046 -> 3252423 (-0.05%); split: -0.05%, +0.00%
CodeSize: 17839104 -> 17680580 (-0.89%); split: -0.89%, +0.00%
Latency: 24424322 -> 24426242 (+0.01%); split: -0.01%, +0.01%
InvThroughput: 10140681 -> 10143882 (+0.03%); split: -0.01%, +0.04%
SClause: 80731 -> 80738 (+0.01%); split: -0.01%, +0.02%
Copies: 293719 -> 293593 (-0.04%); split: -0.27%, +0.23%
Branches: 126625 -> 126626 (+0.00%); split: -0.00%, +0.00%
VALU: 2086026 -> 2086029 (+0.00%)
SALU: 502641 -> 501012 (-0.32%); split: -0.33%, +0.00%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30902>
 2024-09-09 19:48:22 +00:00
Daniel Stone
ed4dc4261e ci/vulkan: Backport dEQP commit to make it less OOMy 
It looks like the compute reconvergence tests are slamming us into OOM
on stoney at least; backport a commit which makes this less horrible.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30978>
 2024-09-09 16:27:07 +00:00
Samuel Pitoiset
868272c2e9 radv: disable shaders linking with ESO when nextStage of VS/TES isn't present 
For example, if the application wants to create linked shaders with
VS/TCS/TES but the next stage of TES isn't present, the driver would
have to compile shader variants (ie. nextStage could be NONE,TES,GS).

This isn't supported by RADV without re-compiling all shaders twice,
and it's also likely less optimal than compiling unlinked shaders.

This fixes recent CTS
dEQP-VK.shader_object.link.linked_linked_linked_unlinked_unlinked.*

Fixes: 37d7c2172b ("radv: add support for creating/destroying shader objects")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31062>
 2024-09-09 11:00:52 +00:00
David Rosca
95d15406c4 radv/video: Don't use multiple tasks for one encode operation 
The begin op was sent as one task and encode op as another one.
This doesn't work on VCN2 and older, so just send both ops in same task.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31078>
 2024-09-09 06:55:03 +10:00
David Rosca
60c38b9886 radv/video: Don't use op_close in encode 
This should only be used on video session destroy, but at that point
we don't have command buffer. RENCODE_IB_OP_CLOSE_SESSION is optional,
so it's okay not using it at all.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31078>
 2024-09-09 06:54:47 +10:00
Marek Olšák
1537b9355a ac,radeonsi: update comments related to the L2 cache, use "L2", not "TC" 
"GL2" is also OK. "TC-compatible" is also OK.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30869>
 2024-09-07 01:51:23 +00:00
Marek Olšák
1b94137039 ac/nir/meta: move the "skip compute if no DCC image stores" condition to common 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30869>
 2024-09-07 01:51:23 +00:00
Marek Olšák
5250128c6a ac: fix WAVES_PER_SH value for gfx12 
not a serious issue because we only use it for PRIME without SDMA IIRC

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30869>
 2024-09-07 01:51:23 +00:00
Alyssa Rosenzweig
1753bf599c ci: update traces 
🤕

thanks Mike

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Samuel Pitoiset
eab5b453cd radv: fix allocating sparse descriptor buffers in the 32-bit addr space 
There are two bugs:
- VK_KHR_maintenance5 added VkBufferUsageFlags2CreateInfoKHR, so
checking for pCreateInfo->usage is incomplete
- this was also missing the usage flag for descriptor buffer with samplers

This fixes recent VKCTS coverage in
dEQP-VK.binding_model.descriptor_buffer.*.

Fixes: 059391b631 ("radv: use 32bit va range for sparse descriptor buffers")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31054>
 2024-09-06 18:27:37 +00:00
Georg Lehmann
6ac576ceb0 radv/ci: update trace checksums 
Single pixel differences that are indistinguishable to my eyes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28676>
 2024-09-06 09:16:21 +00:00
Timur Kristóf
6e000d2817 radv: Determine linked I/O info after nir_opt_varyings. 
This makes it possible to not allocate I/O space
(such as LDS or VRAM) for I/O slots that were eliminated
by nir_opt_varyings.

Fossil DB stats on Rembrandt:

Totals from 896 (1.13% of 79395) affected shaders:
MaxWaves: 19452 -> 19488 (+0.19%)
Instrs: 443693 -> 443711 (+0.00%); split: -0.01%, +0.01%
CodeSize: 2331788 -> 2330904 (-0.04%); split: -0.04%, +0.01%
VGPRs: 43088 -> 42992 (-0.22%)
Inputs: 10344 -> 9198 (-11.08%)
Outputs: 7991 -> 6845 (-14.34%)
LDS: 3537408 -> 3184128 (-9.99%)
Latency: 1636786 -> 1636899 (+0.01%); split: -0.01%, +0.01%
InvThroughput: 359066 -> 358825 (-0.07%); split: -0.08%, +0.01%
VClause: 12106 -> 12109 (+0.02%); split: -0.02%, +0.05%
SClause: 6770 -> 6766 (-0.06%); split: -0.07%, +0.01%
Copies: 26532 -> 26540 (+0.03%); split: -0.02%, +0.05%
PreVGPRs: 32345 -> 32342 (-0.01%); split: -0.01%, +0.00%
VALU: 288476 -> 288501 (+0.01%); split: -0.00%, +0.01%
SALU: 44527 -> 44530 (+0.01%); split: -0.00%, +0.01%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28676>
 2024-09-06 09:16:21 +00:00
Timur Kristóf
17f6ab28cc radv: Add new linking step and use nir_opt_varyings. 
The nir_opt_varyings pass is the new NIR solution for shader
linking, with new features including better I/O compaction,
packing 16-bit I/O, inter-stage code motion and more.

Fossil DB stats on Rembrandt:

Totals from 34585 (43.56% of 79395) affected shaders:
MaxWaves: 873362 -> 873260 (-0.01%); split: +0.11%, -0.12%
Instrs: 21543639 -> 21526956 (-0.08%); split: -0.27%, +0.19%
CodeSize: 115077568 -> 115015536 (-0.05%); split: -0.25%, +0.20%
VGPRs: 1465152 -> 1464192 (-0.07%); split: -0.29%, +0.22%
Inputs: 161776 -> 158711 (-1.89%); split: -1.90%, +0.00%
Outputs: 46532551993 -> 46532548680 (-0.00%); split: -0.00%, +0.00%
LDS: 70597120 -> 70794752 (+0.28%); split: -0.04%, +0.32%
Latency: 162963576 -> 162785055 (-0.11%); split: -0.25%, +0.14%
InvThroughput: 37356298 -> 37261700 (-0.25%); split: -0.37%, +0.12%
VClause: 427827 -> 427105 (-0.17%); split: -0.35%, +0.18%
SClause: 669989 -> 668623 (-0.20%); split: -0.36%, +0.15%
Copies: 1582166 -> 1582592 (+0.03%); split: -0.36%, +0.39%
Branches: 523203 -> 523789 (+0.11%); split: -0.04%, +0.15%
PreSGPRs: 1272992 -> 1273228 (+0.02%); split: -0.05%, +0.07%
PreVGPRs: 1164295 -> 1161623 (-0.23%); split: -0.43%, +0.20%
VALU: 13733432 -> 13714109 (-0.14%); split: -0.35%, +0.21%
SALU: 2828974 -> 2831841 (+0.10%); split: -0.12%, +0.22%
VMEM: 748396 -> 748500 (+0.01%); split: -0.16%, +0.18%
SMEM: 1263487 -> 1263329 (-0.01%); split: -0.03%, +0.02%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28676>
 2024-09-06 09:16:21 +00:00
Timur Kristóf
fcb2c62b63 radv: Add NIR XFB IO intrinsic info to legacy stages not just NGG. 
Some NIR passes (such as nir_opt_varyings) rely on having the
XFB info in explicit I/O intrinsics. If we want to use those,
we need to add this info.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28676>
 2024-09-06 09:16:21 +00:00
Timur Kristóf
79df320463 ac/nir: Move varying cost functions from radeonsi to common code. 
This code will be shared between RADV and RadeonSI.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28676>
 2024-09-06 09:16:21 +00:00
Samuel Pitoiset
5fd3be6f1b radv: stop relying on the VS for emitting VBO descriptors in DGC 
This is required for experimenting indirect graphics pipelines with DGC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Samuel Pitoiset
53c760c388 radv: pass vb_desc_usage_mask in radv_dgc_params 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Samuel Pitoiset
4bd4f037b5 radv: emit all VBO descriptors in the prepare DGC shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Samuel Pitoiset
8397e15019 radv: use radv_vbo_info for emitting descriptors with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Samuel Pitoiset
a1646f468d radv: compute rsrc3 for VBO descriptors in NIR for DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Samuel Pitoiset
91fdce3f5a radv: add a helper to get VBO info for emitting descriptors 
This will be used to rework VBO in DGC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Timur Kristóf
4d5bc893b4 ac/nir/tess: Remove no_inputs_in_lds. 
When there are no VS outputs, we expect that the drivers set
the LS-HS vertex stride to zero, which will produce the
same result as no_inputs_in_lds did.

Remove the unnecessary code path from the output lowering.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30962>
 2024-09-05 19:54:29 +00:00
Marek Olšák
52c41f25de ac/nir/tess: don't allocate LDS for HS inputs that are passed via VGPRs 
Right now we don't allocate LDS for HS inputs when all HS inputs are passed
via VGPRs.

This changes it to skip allocating exactly the HS inputs passed via VGPRs
by reducing the inputs_read mask to remove holes.

radeonsi changes to the LDS allocation will be in a different MR.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30962>
 2024-09-05 19:54:29 +00:00
Samuel Pitoiset
165c026161 radv: add a helper to write a single vertex descriptor with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31018>
 2024-09-05 10:29:55 +00:00
Samuel Pitoiset
374abea26b radv: pass use_per_attribute_vb_descs in radv_dgc_params 
This is more like a shader metadata parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31018>
 2024-09-05 10:29:55 +00:00
Samuel Pitoiset
955f148db1 radv: specialize one more VBO parameter with DGC 
This covers the case when unused VBO bindings are defined with DGC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31018>
 2024-09-05 10:29:55 +00:00
Samuel Pitoiset
e99ea580f7 radv: fix missing attribute offset with dynamic VS inputs and DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31018>
 2024-09-05 10:29:55 +00:00
Mike Blumenkrantz
cd7ad7bd7e vk: rename DGC feature to DGC-NV 
this is an NV extension, so it should have NV suffix

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31015>
 2024-09-04 12:27:21 +00:00
Samuel Pitoiset
63112e79ac radv: use compute pipeline metadata for non-indirect DGC pipelines 
The idea is to better abstract loading shader metadata parameters by
using the same layout for indirect/non-indirect compute pipelines.

Graphics support will added later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30987>
 2024-09-04 06:50:38 +00:00
Samuel Pitoiset
9a07b8fa1c radv: store the indirect compute pipeline VA to dgc_cmdbuf 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30987>
 2024-09-04 06:50:38 +00:00
Samuel Pitoiset
81ec193e1b radv: specialize dispatch initiator for compute/task shaders with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30987>
 2024-09-04 06:50:38 +00:00
Samuel Pitoiset
fbb1ed66e4 radv: stop storing DGC info as part of the VBO descriptors 
This is no longer needed and it's possible to just load&store the
bindings that aren't updated by DGC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30918>
 2024-09-04 06:17:37 +00:00
Samuel Pitoiset
57aa34a30d radv: pass more VBO info as parameters to the DGC prepare shader 
Instead of storing the stride/rsrc_word3 as part of the VBO descriptors,
pass them as parameters. This is cleaner and this will allow us
to simplify VBO in DGC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30918>
 2024-09-04 06:17:37 +00:00