It might happen that a raw data object (from pipeline cache creation)
was never looked up, and thus never deserialized, before it gets
inserted again into the cache. In this case, the deserialized object
got replaced by the raw data object.
Instead, replace the raw data object with the real object in the cache.
Fixes: 8b13ee75ba ('vulkan: Fall back to raw data objects when deserializing if ops == NULL')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22735>
We do not support stream outputs yet so be better at faking it.
Fixes the following assertion when running deqp-gles3:
u_blitter.c:635: blitter_check_saved_vertex_states: Assertion `!ctx->has_stream_out || ctx->base.saved_num_so_targets != ~0u' failed
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22754>
From the Vulkan spec (§11.2.13. Freeing Device Memory):
If a memory object is mapped at the time it is freed, it is implicitly
unmapped.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22762>
For indirect draw commands the data segment's address was being
calculated with an unaligned code size which could potentially
send an unaligned address to the hw causing problems.
Reported-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22746>
The code to increment the destination buffer address was wrong. Instead of
incrementing an address on every iteration, the buffer slice size was added
as a static offset to all blits.
Seen in dEQP-VK.draw.renderpass.depth_clamp.d16_unorm, though issues remain.
Signed-off-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22747>
When pvr_graphics_pipeline_alloc_vertex_special_vars() was
allocating vtxin regs for special vars, it wasn't returning back
the updated amount of allocated regs so when the PDS was filling
them in, it would try to write out of bounds.
Signed-off-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22750>
Depth/stencil surfaces are not PBE renderable, so a compatible format must
be used instead. The code to calculate this compatible format was not called
when configuring the PBE, and it was missing formats.
Also the code to calculate PBE swizzles was throwing an error in unhandled
cases, rather than using the pre-calculated defaults which was the correct
behaviour.
Fixes blits in dEQP-VK.draw.renderpass.depth_clamp.d32_sfloat
Signed-off-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22748>
We need to do full pow if 64-bit, and we can do fpow() otherwise. Not
the other way around.
Fixes: 9076c4e289 ("nir: update opcode definitions for different bit sizes")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22774>
The Vulkan spec says:
"If the depth clamping state is changed dynamically, and the pipeline
was not created with VK_DYNAMIC_STATE_DEPTH_CLIP_ENABLE_EXT enabled,
then depth clipping is enabled when depth clamping is disabled and
vice versa"
Fixes: e48c0fbd8f ("radv: add support for dynamic depth clamp enable")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22777>
The flag was ignored for VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT and
VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT.
Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22781>
It should work but if not enabled by default, I think most people
forget about it.
If you have any issues with it, you can disable by using
RADV_THREAD_TRACE_CACHE_COUNTERS=false and please report!
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22763>
1D texture miplevels are aligned to 64b, but this should include also
texture arrays.
Fixes
`spec@glsl-1.30@execution@texelfetchoffset@vs-texelfetch-usampler1darray`
and several other piglit tests.
CC: mesa-stable
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22775>
The check for max_dw means that none of checks triggered reliably
when we had an issue. Use a stricter reserved dw measure to increase
the probability of catching issues.
Adds a radeon_check_space to some places after cs_create as they
previously relied on the min. cs size, but that would still trigger
the checks.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20152>
Removes duplicate ARL reads from the same source when the original ADDR
register is still live. This is the remaining low-hanging fruit from #7723
Should account for most of the potential improvements and is also
trivial as no source or destination rewrite is needed.
RV530:
total instructions in shared programs: 132447 -> 131488 (-0.72%)
instructions in affected programs: 33396 -> 32437 (-2.87%)
helped: 331
HURT: 0
total temps in shared programs: 17035 -> 17015 (-0.12%)
temps in affected programs: 361 -> 341 (-5.54%)
helped: 30
HURT: 10
RV370:
total instructions in shared programs: 83555 -> 82659 (-1.07%)
instructions in affected programs: 28310 -> 27414 (-3.16%)
helped: 312
HURT: 0
total temps in shared programs: 12418 -> 12426 (0.06%)
temps in affected programs: 302 -> 310 (2.65%)
helped: 21
HURT: 29
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22752>
There's little point in going from fixed-function to ARB progs just to
convert it to NIR in the end. So let's emit NIR code directly here
instead.
This all made sense back when we had DRI drivers that didn't use NIR at
all in the tree, but these days we unconditionally call prog_to_nir.
Since we're no longer generating something that resembles ARM asm
shaders, we also no longer pass is_arb_asm as true to NewProgram. But
we still require legacy math rules, so we set use_legacy_math_rules in
the shader_info instead. This should do the same thing, but
communicates exactly what we actually need rather than having a half-
truth about the source of the shader.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22520>
