Functions (i.e. labels reached from call instructions) should be printed
differently from normal labels. In addition we also need to add support
for entrypoints with user-defined names in order to show packet names in
afuc.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23949>
In afuc, we have the situation where there are a number of ALU
instructions with two (almost) completely different encodings, including
a different opcode location, etc. These need to be different leaf
bitsets with different names for the encoder to work, because otherwise
the encoder has no way of descriminating between them, but when
displaying them we want to use the same name. This adds a small facility
to make the name used for {NAME} when displaying and for the opcode
when encoding different, so that e.g. OPC_ADDI can display as "add"
instead of "addi".
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23949>
This allow us to remove one more i915_drm.h include from code shared
by both backends.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23905>
This I915_EXEC_FENCE_SIGNAL was missed in the conversion from i915_drm.h
types to IRIS ones.
Both have the same value, so it was not causing any issues.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23905>
Only hwconfig was calling i915 specifc function, so it was only
necessary split the function that fetches it from backends and call it
from intel_get_and_print_hwconfig_table() depending on the KMD loaded.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23905>
Calling the ra_allocate function after each register spill can take
several minutes. This option speeds up shader compilation by spilling
more registers after the ra_allocate failure.Required for
Cyberpunk 2077, which uses a watchdog thread to terminate the process
in case the render thread hasn't responded within 2 minutes.
Execution time of my Cyberpunk2077 shader compilation test:
https://gitlab.freedesktop.org/illia.a.polishchuk/cyberpunk-vulkan-compute-hang-test-anv
Before the patch:
real 1m28,738s
user 1m28,329s
sys 0m0,400s
After the patch
real 0m33,245s
user 32m,835s
sys 0m0,404s
I think it's acceptable patch because Cyberpunk benchmarks has
the same FPS with and without patch. (I started
it without patch with a patched binary with disabled watchdog thread)
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Requires: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24228
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9241
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24299>
This prepares for allowing to compile 1 shader at a time
for merged shader stages.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23874>
This is necessary to initialize context and mark all the state as
dirty so it is re submitted.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24336>
a variable with a component offset may span multiple slots, and this cannot
be inferred from its type alone (e.g., compacted clip+cull distances)
cc: mesa-stable
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24163>
We always have this extension available to us, since we demand matching
Mesa builds, and it's much better. Just use it always when we're not on
swrast.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24347>
We don't need this anymore; the image loader extension does everything
we want it to and more, and is mandatory when we load.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24347>
We already look up the image driver extension inside
dri2_core_extensions, so don't do it again in the optional extensions -
just do it in the swrast path so we have it covered for both.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24347>
Add support for 1555 and 4444 formats, both in RGB/BGR ordering, with
and without alpha.
These are already supported by Gallium and drivers, but not yet for
winsys surfaces. Adding these is enough to make them renderable when
using Weston on iris.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24331>
With shader object, if TES is compiled without a TCS, the number of
TCS vertices out might not be known at compile time and it needs to be
loaded from a user SGPR.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24346>
It only contains the number of tessellation patches for now, but it
will be used to pass the number of TCS vertices out for shader object.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24346>
This is only needed when the number of patch control points is known
at compile time. Adding a check makes it less confusing.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24346>
This allows geometry shaders to work with shader object on GFX6-8
because the workgroup size is the wave size. We will need different
tweaks for NGG but that's for later.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24333>
This implements fixed IO location for VS/TES with GS. This is currently
unused because everything is linked with GPL or monolithic pipelines,
but this will be used for shader object.
Tested by running full CTS after disabling NIR IO linking for VS/TES.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24328>
This partially reverts commit da54b578.
Vulkan spec defers the definition of these lists to the H265 ITU spec,
which defines the scaling lists to be in "up-right diagonal scan order"
already.
Fixes: da54b578 ("radv/video: fix hevc scaling lists.")
Reviewed-by: Lynne <dev@lynne.ee>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24356>
Before this patch, when updating the indirect clear color, BLORP only
invalidated the texture cache on gfx11. The hardware docs state that
the texture cache invalidation is also needed on gfx12 however. Add
this invalidation for gfx12 and move the fast-clear related cache
invalidations to the drivers for clarity and performance.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5850
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23588>
In GL and a lot of Vulkan if we end up with either a lod or an ms index.
Sadly in Vulkan we can end up with both and have to choose properly. For
TXQ we have to emit a zero LOD. For TXF we have to emit the ms index.
Fixes: bb032d8b62 ("nv50/ir/nir: implement nir_instr_type_tex")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24343>
