Commit graph

160297 commits

Author SHA1 Message Date
Sil Vilerino
45e9e2693d d3d12: Export some util functions from d3d12_fence for d3d12 video
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
ed329865ba d3d12: Change type of m_FenceValue to uint64_t in d3d12_video_encoder
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
9fb3b2ab12 d3d12: Add support for PIPE_VIDEO_CAP_ENC_SUPPORTS_ASYNC_OPERATION
Add support for PIPE_VIDEO_CAP_ENC_SUPPORTS_ASYNC_OPERATION based on D3D12_VIDEO_ENC_ASYNC env variable defaulted to true

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
fe2b28192f d3d12: Report PIPE_VIDEO_CAP_REQUIRES_FLUSH_ON_END_FRAME
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
a92cfd5c88 d3d12: Add initialization values for d3d12_video_encoder
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
020c0af732 d3d12: Video process - Remove unnecessary batches flush
Make resident and sync in flush() method instead of before to avoid extra batch flushes

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
b47b9d96fd d3d12: Update HEVC Encode GOP on I frames too
Update GOP also on I HEVC frames in d3d12_video_encoder_update_hevc_gop_configuration

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
229c6f79a6 frontends/va: Implement vaSyncBuffer
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Georg Lehmann
84c0529258 aco: Unswizzle v_pk_fma_f16 literals to produce more v_pk_fmac_f16.
No Foz-DB difference, but it reduces code size in some angle shaders.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18676>
2022-09-21 23:04:06 +00:00
Jonathan Gray
ed5d16cec1 iris: check i915 features after hw gen
when running recent Mesa on i855 (gen 2) without amber drivers:
  error: Kernel is too old for Iris. Consider upgrading to kernel v4.16.

  libGL error: glx: failed to create dri3 screen
  libGL error: failed to load driver: iris
  error: Kernel is too old for Iris. Consider upgrading to kernel v4.16.

  libGL error: glx: failed to create dri2 screen
  libGL error: failed to load driver: iris

move the i915 feature check to after the hardware generation check
which results in:
  MESA: warning: Driver does not support the 0x3582 PCI ID.
  libGL error: glx: failed to create dri3 screen
  libGL error: failed to load driver: iris
  MESA: warning: Driver does not support the 0x3582 PCI ID.
  libGL error: glx: failed to create dri2 screen
  libGL error: failed to load driver: iris

Cc: mesa-stable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18563>
2022-09-21 22:38:33 +00:00
Brian Paul
4e2d88781d gallivm: fix nir AOS swizzling issues
The nir code for AOS (aka linear) mode had a number of issues.

In some cases, the RGB->BGR swizzling wasn't happening, leading to
incorrect colors.  In other cases, bad swizzling caused the first
pixel's color to be written to four adjacent pixels.

Writemasks must also be swizzled.  For example, if an instruction's
writemask indicates the X component but the AOS component order is
BGRA we need to change the writemask to Z.

Another issue was with constant buffer values not getting consistently
convert to BGRA order.  Fixing this involves removing the
lp_nir_aos_conv_const() function and immediately converting immediate
values from 4 x f32 in [0,1] to 16 x u8 when we translate nir's
load_const so that we know the value is in the right linear/AOS layout
right away.

Finally, the llvmpipe_nir_fn_is_linear_compat() function was not
checking that nir_instr_type_load_const values are in [0,1] for AOS
execution.  The info.unclamped_immediates field is not needed for
the NIR path (but still used for the old TGSI path).

This fixes quite a few tests in our VMware suite.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
d82abf448d gallivm: asst. clean-ups in lp_bld_sample_soa.c
Wrap lines to 78 chars.  Move var decls to where they're first used.
Etc.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
a4ce5d74d7 llvmpipe: asst. formatting, clean-ups in lp_state_fs.c
Wrap lines to 78 chars.  Move var decls to where they're first used.
Etc.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
bd7ed4c6a2 gallivm: change texture/sampler_index params to unsigned
To match other functions taking those params.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
9b86745d69 gallivm: move lp_build_nir_aos_context declaration, etc
Move the lp_build_nir_aos_context struct declaration and
lp_nir_aos_context() cast wrapper from lp_bld_nir.h to
lp_bld_nir_aos.c and use the cast wrapper in more places.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
2967cc25ea util: allow GALLIUM_LOG_FILE=stdout
To log gallium info to stdout instead of a file.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
69f7c91fe9 llvmpipe: always pass non-zero writemask to assign_reg()
Removes an uneeded conditional expression.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
9fbb77445c llvmpipe: further bump LP_MAX_TGSI_SHADER_IMAGES to 64
I previously bumped this to 32, but we need at least 64 to pass
a few other VMware tests (e.g. dx11-slots-uav-write-vs-gs-all-64).

Also update/generalize a comment.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
ce65c7f0e9 lavapipe: s/u_foreach_bit/u_foreach_bit64/ in handle_pipeline_access()
Since the lvp_access_info fields are uint64_t.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Chia-I Wu
79208d8bf3 turnip: advertise VkExternalFenceProperties correctly
Remove tu_GetPhysicalDeviceExternalFenceProperties and let the common
entrypoint does the work.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18711>
2022-09-21 20:55:41 +00:00
Mike Blumenkrantz
2569215f43 egl/glx: add fallback for zink loading
if the driver attemping to load is not zink and not software, then
attempt a zink fallback on failure

this conservatively handles the case of "only zink is built", though it
is going to be noticeably slower at startup than loading zink directly

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16168>
2022-09-21 20:29:06 +00:00
Emma Anholt
112b8d7c4d ci/zink+turnip: Add a manual full run of the dEQP CTS.
We don't have enough spare boards to run this by default, but it's
catching interesting bugs and we want to be able to look at its status for
evaluating zink usage.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18717>
2022-09-21 19:57:07 +00:00
Samuel Pitoiset
578e30f3e6 radv: make sure to initialize wd_switch_on_eop before checking its value
This is technically not a bug because it might just trigger
SWITCH_ON_EOI when streamout is used and I think it was fine.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7303
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18700>
2022-09-21 18:20:58 +00:00
Emma Anholt
64d0e94d2c turnip: Use the simplified stencil write flags for the LRZ-allowed check.
Traces of GLES games that ANGLE has taken frequently have no-op stencil
writes, which ANGLE and Zink both pass straight through.  Given that we
support dynamic stencil state updates via tu_CmdSetStencil*(), draw time
really is the time for deciding this state unfortunately.

Reuse the fancier stencil write enables check from "can we do early z?" in
"can we do LRZ?".  This gets one set of draws in among_us to have LRZ, but
I don't see a detectable performance difference.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18691>
2022-09-21 17:18:07 +00:00
Emma Anholt
b9f9bfa556 turnip: Fix the "written stencil is unmodified" check.
We want to know if anything writes stencil, not if all of them do.

Fixes: b2a60c157e ("turnip: add LRZ early-z support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18691>
2022-09-21 17:18:07 +00:00
Timur Kristóf
ed76471d08 aco/optimizer_postRA: Clarify terminology.
Change the terminology around the post-RA optimizer, primarily this
changes the use of "clobbered" to "overwritten" to avoid confusion,
and it removes some redundant states.

Proposed for backporting to stable, to make sure it is easy to
backport further fixes (if any) on top of this.

Fossil DB stats unaffected on Navi 21.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18488>
2022-09-21 16:56:57 +00:00
Timur Kristóf
a8dd07518c aco/optimizer_postRA: Fix logical control flow handling.
Change reset_block() so it only considers the logical
predecessors for VGPRs. Relevant for some optimizations
across loops.

This commit fixes an assertion failure which was triggered
by Zink in a piglit test.

Fossil DB stats unaffected on Navi 21.

Fixes: 2e56e23420
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18488>
2022-09-21 16:56:57 +00:00
Timur Kristóf
2eab413cf7 aco/optimizer_postRA: Don't assume all operand registers were written by same instr.
This assumption is no longer true since the post-RA optimizer
can work across blocks. It is now possible that some control
flow paths overwrite some but not all registers of an operand.

This commit may prevent invalid optimizations and/or assertion
failures (on debug builds).

Fossil DB stats unaffected on Navi 21.

Fixes: 0e4747d3fb
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18488>
2022-09-21 16:56:57 +00:00
Timur Kristóf
63063dd5ce aco/optimizer_postRA: Mark a register overwritten when predecessors disagree.
Affects blocks whose some (but not all) predecessors overwrite a register.
This commit fixes glitches in some games which regressed because of the
improved SCC no-compare optimization.

Fossil DB stats on Navi 21:

Totals from 2816 (2.09% of 134906) affected shaders:
CodeSize: 24224276 -> 24241580 (+0.07%)
Instrs: 4570595 -> 4574921 (+0.09%)
Latency: 53680256 -> 53693655 (+0.02%); split: -0.00%, +0.02%
InvThroughput: 9829289 -> 9830573 (+0.01%)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7257
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7305
Fixes: 2e56e23420
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18488>
2022-09-21 16:56:57 +00:00
Timur Kristóf
5e80edfa78 aco/tests: Add post-RA SCC no-compare tests cases with control flow.
- scc_nocmp_across_cf: passes
- scc_nocmp_across_cf_partially_overwritten: fails (fixed later)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18488>
2022-09-21 16:56:56 +00:00
Timur Kristóf
d4b3f81d94 aco/tests: Add post-RA DPP test cases with control flow.
These are intended to make sure that the post-RA optimizer works
correctly across control flow. The new tests emit a divergent
if-else branch (with full logical+linear CFG).

- dpp_across_cf:
  Simple case of DPP optimizable across control flow. Should pass.
- dpp_across_cf_overwritten:
  Similar case but the DPP source register is overwritten in CF.
  This shows a bug so the test fails now (will be fixed).

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18488>
2022-09-21 16:56:56 +00:00
Timur Kristóf
d7cd49d54b aco/tests: Add post-RA optimizer testcase for partially overwritten VCC.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18488>
2022-09-21 16:56:56 +00:00
Karmjit Mahil
c4fa00f751 pvr: Add EMIT_MASK in pvr_emit_ppp_state().
This commit adds an extra check on the emitted ppp state by
adding an EMIT_MASK.
The mask is just a copy of the header at the beginning of the emit.
Each time a word is emitted the appropriate bit in the mask is
cleared and at the end we make sure that the mask is 0. If not,
we forgot the either clear a bit somewhere or emit some words.
This is intended to make it easier to find such errors.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18631>
2022-09-21 16:47:06 +00:00
Karmjit Mahil
1cfcf86da4 pvr: Add assert for texturestate being 0 in when emitting ppp state.
We assume that the texturestate size is 0 so we don't emit a state
update for pds_state_ptr2 since the hw wouldn't use it based on
the 0 size. This commit adds an assert to make sure of that.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18631>
2022-09-21 16:47:06 +00:00
Matt Coster
38a846ab5f pvr: Add pvr_csb_unpack().
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Co-Authored-By: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18631>
2022-09-21 16:47:06 +00:00
Karmjit Mahil
a1c66ed5c1 pvr: Complete pvr_emit_ppp_state().
This commit appends dbsc commands to be executed in secondary
command buffers on vkCmdExecuteCommands().

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18631>
2022-09-21 16:47:06 +00:00
Karmjit Mahil
ad4886cea9 pvr: Make control stream word writing stricter.
Use pvr_csb_write_value() and pvr_csb_write_struct() to have some
extra checks when writing pre-packed command/state words in
pvr_emit_ppp_state().

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18631>
2022-09-21 16:47:06 +00:00
Karmjit Mahil
b5cbbdba29 pvr: Add csb helpers macros to write into raw buffer.
This commit adds two helper macros to write control stream words
into raw buffers with some extra checks.
The new macros are renamed versions of the previous CS_WRITE() and
CS_PACK_WRITE() macros.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18631>
2022-09-21 16:47:06 +00:00
Karmjit Mahil
091a117e38 pvr: Remove struct pvr_emit_state and emit header directly.
Previously `struct pvr_emit_state` was used to keep track of which
state update required emitting and the header was setup based on that.
This commit removes it so that we're instead setting up the header as
we go and we can emit it directly instead of decoding it based on the
emit_state (which is almost identical but with a few missing fields).

This commit also changes pvr_emit_ppp_state() so that each control
stream word is packed/emitted on its own instead of everything
being nested within the header pack. Making the code a bit easier
to follow.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18631>
2022-09-21 16:47:06 +00:00
Rajnesh Kanwal
75b57f44c1 pvr: Implement vkResetEvent API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18708>
2022-09-21 16:36:18 +00:00
Rajnesh Kanwal
96f5892f62 pvr: Implement vkSetEvent API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18708>
2022-09-21 16:36:18 +00:00
Timur Kristóf
2274b26dfb ac/nir/ngg: Don't initialize same-invocation mesh shader outputs.
This is actually not necessary and generates a lot of superfluous
instructions at every phi (setting the value to zero).

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18566>
2022-09-21 16:14:59 +00:00
Timur Kristóf
697ea02202 ac/nir/ngg: Don't use LDS for same-invocation indices and cull outputs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18566>
2022-09-21 16:14:59 +00:00
Timur Kristóf
bb4bdba17e radv: Remove dead shader temps after linking.
Prevent nir_lower_scratch accidentally turning these dead variables
into scratch. This can especially happen to arrayed outputs of
eg. tess control or mesh shaders, which become large shader temps.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18566>
2022-09-21 16:14:59 +00:00
Timur Kristóf
3e6ad428b6 radv: Change max preferred task workgroup invocations to 64.
This was accidentally left at the maximum possible value.
However I now tested this with the cadscene demo app and there is
hardly any benefit from going above 64. Set it to 64 for now.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18566>
2022-09-21 16:14:59 +00:00
Daniel Schürmann
98e3c446d8 aco/optimizer: disallow can_eliminate_and_exec() with s_not
Totals from 295 (0.22% of 134913) affected shaders: (GFX10.3)
CodeSize: 1016564 -> 1016896 (+0.03%); split: -0.05%, +0.09%
Instrs: 187659 -> 187724 (+0.03%); split: -0.08%, +0.11%
Latency: 2839516 -> 2839541 (+0.00%); split: -0.01%, +0.01%
Copies: 12301 -> 12305 (+0.03%); split: -0.01%, +0.04%
PreSGPRs: 10266 -> 10268 (+0.02%)

Closes: #7024
Cc: mesa-stable
Tested-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18722>
2022-09-21 15:33:43 +00:00
Marek Olšák
d6fabe49cd radeonsi: enable glthread by default
Let's enable it and see what happens. This should mostly be a win.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
2022-09-21 14:54:50 +00:00
Marek Olšák
4ff207b47b glthread: execute glSignalSemaphoreEXT synchronously
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
2022-09-21 14:54:50 +00:00
Marek Olšák
da68678171 radeonsi: don't flush asynchronously for fence_server_signal
See the comment.

Fixes: 21b3a234 - mesa: fix SignalSemaphoreEXT behavior

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
2022-09-21 14:54:50 +00:00
Marek Olšák
000dfb1bc9 radeonsi/ci: add glx@glx-swap-event_async to CI failures for glthread
The test can't pass because glXSwapBuffers now executes GL functions,
which the test doesn't expect. It's a test defect IMO.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
2022-09-21 14:54:50 +00:00