Commit graph

957 commits

Author SHA1 Message Date
Alyssa Rosenzweig
82597c46c3 pan/bit: Add mode to run unit tests
Probably the most useful of the bunch going forward.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
1a1c55709e pan/bit: Make run more useful
..by printing some output.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
50476efb61 pan/bit: Add csel tests
..and pull out common instruction generation to reduce duplication in
tests a bit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
9b262208b6 pan/bit: Add CSEL to interpreter
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
069189ff0f pan/bit: Add FMA tests
Now that the earlier reg ctrl issue is fixed these should pass.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
78ba6d50a4 pan/bit: Add 16-bit fmod tests
These raise another set of issues -- indeed, not all of these tests are
passing, since it turns out I have an actual bug in the packing code. So
after all this work, test bringup has identified an actual issue :)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
40160c576d pan/bit: Add verbose printing for tests
We'd like to dump both the generated IR (so we know exactly what's being
tested) as well as the compiled program (so we know what's running for
comparison).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
7c887d368e pan/bit: Add helper for generating floating mod tests
We can iterate them, isn't that adorable!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
14c5343867 pan/bit: Add packing test framework
Given an instruction, we'd like to wrap it in a clause with some I/O on
each end so we can pack it up and send it to the hardware to compare
against the simulator.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
5e3e32e368 pan/bit: Implement floating source mods
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
dbb8a564f2 pan/bit: Implement outmods
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
ab58185604 pan/bit: Add preliminary FMA/ADD/MOV implementations
Missing some details about modifiers but the core structure should
look like this for 32 and 16-bit, I think. My sincerest apologies for
the macro magic, I tried to make it the least bad I could but trying to
keep down repitition.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
fbe504e221 pan/bit: Handle read/write
We case the various sources and destinations to model register file
access and passthrough in particular.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
7904a29340 pan/bit: Stub out BIR interpreter
We'd like to step through a BIR program to evaluate it for testing.
Let's stub out some infrastructure for modeling Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
8eefb2765a pan/bi: Match CSEL argument order with hw
It turns out ports need to be in order of the arguments of an
instruction (port 3, that is), which breaks on instructions whose IR
argument order is different from the packed order, like csel. So fix
that.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
9114ebbe79 pan/bi: Add helper to debug port assignment
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
0ab3f687c0 pan/bi: Handle BIFROST_FIRST_WRITE_FMA_P2_READ_P3
It's a special case for unclear reasons, and if you mess it up you get
INSTR_INVALID_ENC. Isn't hardware fun?

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
75aabc6ea1 pan/bi: Allow BI_FMA to take mods
It doesn't take abs but it can take outmod/neg.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
69dde49f80 pan/bi: Don't gobble zero ports
In case we've reading/writing R0.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
c7a6df4638 pan/bi: Fix negation in ADD.v2f16
When we flip the sources we need to flip the negates as well to stay
consistent.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
5f48caf98b pan/bi: Fix duplicated source in ADD.v2f16
Typo.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
08fe1081b7 pan/bi: Export bi_class_name
For use in naming tests.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Icecream95
319158a814 pan/midgard: Fix a divide by zero in emit_alu_bundle
util_dynarray_grow_bytes divides by eltsize, but it's possible for
bundle->padding to be zero.

I changed the other call to util_dynarray_grow_bytes for consistency.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4397>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4397>
2020-04-03 16:49:04 +00:00
Alyssa Rosenzweig
1b16d6354b pan/bi: Fix outmod/roundmode flip
I misread the disassembler, the fields are in the other order.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
12cf9f43f0 pan/bi: Handle fmov class ops
We need to lower them to something reasonable (ideally, the modifier
would be attached but we need to do something for the case it's not). We
specifically have to lower pre-sched as well, but we can do the lower
literally at schedule time for now (if this proves annoying, we can move
it earlier, but I want to leave room for modifier-aware copyprop should
that prove interesting).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
357b8b5906 pan/bi: Fix unused port swapping
Fixes INSTR_INVALID_ENC

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
b150fa214b pan/bi: Add cmdline option for verbose disassembly
Useful for debugging packing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
ae4f48b2bc pan/bi: Don't set the back-to-back bit yet
This is bad for performance but we can't assume it's true without some
analysis, which we presently don't do. Leave it for future work and
don't break the present.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
0b241c70b6 pan/bi: Use STAGE srcs for scheduler nops
..rather than using port 0 for the source, which may or may not actually
exist.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
2292e2aa10 pan/bi: Fix writes_component for VECTOR
I'm not convinced this is the best way and it's sort of a hack, but it
fixes RA for st_vary.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
b033189dd7 pan/bit: Wire through I/O
We'd like to wire in attributes and uniforms as inputs and look at the
varying as output for automatic testing on-device, building up a test
framework for us.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
b26214e907 pan/bit: Add run mode to the cmdline
This emulates the functionality of shader_runner (built for kbase) using
the bifrost testing infrastructure so it runs on mainline. Ideally this
will let us test shaders from the assembler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
02ad147c5c pan/bi: Fix handling of constants with COMBINE
We should never see COMBINE constants explicitly since they'll become
moves anyway, so we can simplify that. On the other hand, we do need the
type information for the lowering to work properly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
bd19e76340 pan/bi: Handle fp16/abs scheduling restriction
See previous commit for the packing side. Here we update the scheduler
to accomodate this. Note we don't actually hit this path yet, but it's
good to be proactive.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
c88f816169 pan/bi: Handle abs packing for fp16/FMA add/min
It's seriously quirky, and all to save a single bit. Alas. It also
introduces an edge case for the scheduler which is a bit annoying.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
ba8e11f0f1 pan/bi: Handle core faddminmax16 packing
This works without the exception of absolute values, which have some...
odd properties to be handled in the next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
12a16f2247 pan/bi: Structify fadd/min/max16
There is some quirky encoding here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
c12a208d78 pan/bi: Add v2f16 versions of rounding ops
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
f81b67b857 pan/bi: Handle round opcodes in frontend
These correspond to various ops routed through BI_ROUND

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
c7170e9742 pan/bi: Assert out i16 related converts for now
Needs more investigation, and GLSL doesn't use it quite yet sadly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
2fd8b2e6d4 pan/bi: Add one-source f32->f16 op
This really has a second op for vectorization but we don't handle this
quite yet...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
197c6414ea pan/bi: Add bifrost_fma_2src generic
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
57a8e6e8d0 pan/bi: Handle standard FMA conversions
These are plain old 1-sources so they're easy to start with.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
499e97b519 pan/bi: Enumerate conversions
There are lots of Bifrost conversion opcodes that can all be emitted
from BI_CONVERT, let's pattern match.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
902f99a45d pan/bi: Expand out FMA conversion opcodes
There are a *lot* of them, with lots of symmetry we can exploit to
simplify the packing logic (but not entirely). Let's add the
corresponding header structs/defines, although we don't actually poke
the disassembler at this stage.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
73715124ea pan/bi: Pack outmod and roundmode with FMA
The fields got missed.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
158f2452f2 pan/bi: Add FMA16 packing
It's like the original FMA packing but with swizzles introduced.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
b5148b6b49 pan/bi: Fix missing type for fmul
We add a zero argument, we want it to align with the size of whatever
the other arguments were for optimization.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
5eb209a05f pan/bi: Finish FMA structures
There were some missing fields for the 32-bit case, and the 16-bit case
has separate packing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
375a7d0f32 pan/bi: Ignore swizzle in unwritten component
Otherwise we can trip the assert for no good reason.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00