Commit graph

147880 commits

Author SHA1 Message Date
Sil Vilerino
da11684e9d d3d12: Add HEVC Decode/Encode
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:19:39 -04:00
Sil Vilerino
f2d172a8be gallium/vl: Rename s_addr variable in vl_idct.c as it conflicts with windows existing inaddr.h keyword definition
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:19:39 -04:00
Sil Vilerino
e0b732e506 gallium/vl: Allow vl_zscan.h to be included from C++
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:19:34 -04:00
Sil Vilerino
8e92c76c34 d3d12/va: Name convention rename PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP to PIPE_VIDEO_CAP_SUPPORTS_CONTIGUOUS_PLANES_MAP
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:19:34 -04:00
Sil Vilerino
427135ea6d frontends/va: Support HEVC caps regarding features, block sizes, prediction direction
Add new pipe structures: PIPE_VIDEO_CAP_ENC_HEVC_BLOCK_SIZES, PIPE_VIDEO_CAP_ENC_HEVC_FEATURE_FLAGS, PIPE_VIDEO_CAP_ENC_HEVC_PREDICTION_DIRECTION
Implement new VA caps VAConfigAttribEncHEVCFeatures, VAConfigAttribEncHEVCBlockSizes, VAConfigAttribPredictionDirection

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:19:34 -04:00
Sil Vilerino
2670756965 frontends/va: Extend single to multiple L0-L1 references for HEVC Encode
Also fixing refactored variable name for L0/L1 lists in drivers/radeonsi to avoid build break.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:19:28 -04:00
Sil Vilerino
56684b85e9 frontends/va: Add HEVC Encode support multi slice and extend pipe args
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:19:23 -04:00
Sil Vilerino
52f23f923e frontends/va: Mark IsLongTerm in HEVC decode args
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:19:18 -04:00
Sil Vilerino
ee62f4d614 frontends/omx: Fill HEVC Decode param IntraPicFlag
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:19:09 -04:00
Sil Vilerino
5efd4bbf7f frontends/vdpau: Fill HEVC Decode param IntraPicFlag
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:19:00 -04:00
Sil Vilerino
c7acd6788e frontends/va: Add HEVC decode args: IntraPicFlag, no_pic_reordering_flag, no_bipred_flag
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:18:44 -04:00
Sil Vilerino
a6e32bf15b frontends/va: Add HEVC decode slice descriptors
Adds HEVC decoded slice descriptors to the pipe interface and also to the VA frontend

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18328>
2022-09-15 11:18:43 -04:00
Martin Roukala (né Peres)
2aa4ed16e2 radv/ci: move some tests from the renoir fail to its flake list
This mirrors the change we made for vega10 (6bbe3c6d3) in August...
Seems like the chances of a PASS are indeed slim, but possible.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18590>
2022-09-15 14:12:07 +00:00
Erik Faye-Lund
ba7e87a03d panfrost: do not fake rgtc-support
Panfrost doesn't expose LATC format support at all, so RGTC
state-tracker level RGTC support is sufficient to drop the fake RGTC
flag on Panfrost.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>
2022-09-15 08:16:01 +00:00
Erik Faye-Lund
df58342f61 mesa/st: enable rgtc extension with fallback
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>
2022-09-15 08:16:01 +00:00
Erik Faye-Lund
f25875ce18 mesa/st: do not fall back to uncompressed for rgtc
This logic doesn't really do what it pretends to; we don't expose the
RGTC features unless we actually have RGTC support. This is about to
change, but for that logic to work, we need to be able to tell if we're
using a fallback-format or not, and we can't do that unless we keep the
format as RGTC.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>
2022-09-15 08:16:01 +00:00
Erik Faye-Lund
1735053de5 mesa/st: implement fallback for rgtc
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>
2022-09-15 08:16:01 +00:00
Erik Faye-Lund
091e6e37c2 mesa/main: add _mesa_unpack_rgtc
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>
2022-09-15 08:16:01 +00:00
Erik Faye-Lund
a6ed406d9f util/format: implement rgtc -> r8 / r8g8 unpack
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>
2022-09-15 08:16:01 +00:00
Erik Faye-Lund
dfbcd94041 util/format: allow unpacking less than a block from rgtc
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>
2022-09-15 08:16:01 +00:00
Erik Faye-Lund
6e1c3e98cd util/format: fix broken indentation
This file had a mixture of tabs and spaces for indent.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>
2022-09-15 08:16:01 +00:00
Erik Faye-Lund
bb7d193ab2 mesa: add format-helper for rgtc
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>
2022-09-15 08:16:01 +00:00
Erik Faye-Lund
d33696a31c mesa/st: add context-flag for rgtc
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>
2022-09-15 08:16:01 +00:00
Samuel Pitoiset
efd8d0f6e7 radv/ci: cleanup lists of failures/flakes
When tests are already in the flakes list, it's useless to mark them
as expected failures.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18592>
2022-09-15 07:49:33 +02:00
Chia-I Wu
65f1baf6c6 turnip: use vk_descriptor_set_layout
Mainly for vk_descriptor_set_layout_{ref,unref}.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18588>
2022-09-14 23:57:03 +00:00
Chia-I Wu
43430fe240 turnip: use vk_buffer
Mainly for vk_buffer_range.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18588>
2022-09-14 23:57:03 +00:00
Rob Clark
2664d59aee freedreno: We really don't need aligned vbo's
The logic was inverted, we don't need aligned for later gens.

Fixes: 60912f1ebd ("freedreno: we don't need aligned vbo's")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18605>
2022-09-14 23:32:26 +00:00
Rob Clark
76fbc8be6d freedreno/drm/virtio: Handle read after upload
If we get CPU access (such as a read) after an upload transfer, we need
to ensure that the host has handled the upload.  Do this by stalling
when the buffer is mapped.  (The previous commit ensures we don't try to
do a pointless upload for an already mapped buffer.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18604>
2022-09-14 22:46:18 +00:00
Rob Clark
8c8e13e3b5 freedreno/drm/virtio: Don't prefer upload for mapped buffers
The upload path is intended to avoid stalling on host in order to mmap
recently allocated buffers.  But if we already had to mmap it, no point
in taking the upload path.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18604>
2022-09-14 22:46:18 +00:00
Rob Clark
e71b0d31aa freedreno/virtio: Don't upload if we have valid range
A transfer that only partially writes the staging buffer could overwrite
valid buffer contents, unless we are told that it is ok to discard the
entire range.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18604>
2022-09-14 22:46:18 +00:00
Emma Anholt
696747c96b mesa: Lower mediump temps and CS shared when the driver supports FP16+INT16.
Typically GLSL mediump lowering will have lowered all the ALU ops
generating the values to 16-bit, and once vars_to_ssa happens the mediump
temps disappear.  However, if they don't disappear (for example, the var
gets indirected and eventually gets lowered to scratch or indirect
lowering), then you don't want the storage upconverted to 32-bit.

Also, if a CS shared var is declared mediump, then storing it as 16 bit
prevents conversions around the load store assuming the ALU ops related to
them are 16 bit.  For gfxbench aztec ruins, the CS shared var sizes are
cut in half, improving overall perf by 0.805549% +/- 0.0953482% (n=6) on
gl-5-normal.

freedreno shader-db:
total instructions in shared programs: 2917577 -> 2917743 (<.01%)
instructions in affected programs: 46141 -> 46307 (0.36%)
total last-baryf in shared programs: 109712 -> 109492 (-0.20%)
last-baryf in affected programs: 638 -> 418 (-34.48%)
total full in shared programs: 190275 -> 190218 (-0.03%)
full in affected programs: 156 -> 99 (-36.54%)
total constlen in shared programs: 492596 -> 492600 (<.01%)
constlen in affected programs: 8 -> 12 (50.00%)

total cat6 in shared programs: 33019 -> 33107 (0.27%)
cat6 in affected programs: 3604 -> 3692 (2.44%)
total stp in shared programs: 3626 -> 3670 (1.21%)
stp in affected programs: 3336 -> 3380 (1.32%)
total ldp in shared programs: 1718 -> 1762 (2.56%)
ldp in affected programs: 1680 -> 1724 (2.62%)
(this is all in aztec ruins)

total sstall in shared programs: 195656 -> 195182 (-0.24%)
sstall in affected programs: 3249 -> 2775 (-14.59%)
total (ss) in shared programs: 52823 -> 52966 (0.27%)
(ss) in affected programs: 1733 -> 1876 (8.25%)
total systall in shared programs: 507928 -> 508687 (0.15%)
systall in affected programs: 103010 -> 103769 (0.74%)
total (sy) in shared programs: 23185 -> 23196 (0.05%)
(sy) in affected programs: 1276 -> 1287 (0.86%)
total waves in shared programs: 435290 -> 435302 (<.01%)
waves in affected programs: 12 -> 24 (100.00%)
total loops in shared programs: 407 -> 405 (-0.49%)
loops in affected programs: 9 -> 7 (-22.22%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18452>
2022-09-14 14:56:26 -07:00
Emma Anholt
7e986e5f04 nir/lower_mediump_vars: Don't lower mediump shared vars with atomic access.
I don't know of any GPUs doing 16-bit atomic accesses, nor do I know of
anybody wanting that in shaders.  But deqp has GLES CTS cases that set
mediump on shared variables, so just skip lowering for those vars.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18452>
2022-09-14 14:56:22 -07:00
Emma Anholt
a1c765a44c freedreno/ir3: Consistently lower mediump inputs to 16-bit (when we can).
If every use was a conversion to 16, then ir3_cf would fold it into the
bary instruction.  But if something had generated a highp comparison of
the mediump input with a mediump op result, it would get stuck as highp,
even though we could have used 16-bit values without upconverting.

This fixes dEQP-GLES2.functional.shaders.algorithm.rgb_to_hsl_fragment on
ANGLE on turnip, closing #7043.  fossil-db results are mixed:

fossil-db:
Totals from 697 (4.65% of 14988) affected shaders:
MaxWaves: 10712 -> 10736 (+0.22%)
Instrs: 82394 -> 83572 (+1.43%); split: -1.31%, +2.74%
CodeSize: 178280 -> 180118 (+1.03%); split: -0.46%, +1.49%
NOPs: 15887 -> 16067 (+1.13%); split: -7.48%, +8.61%
MOVs: 1297 -> 1328 (+2.39%); split: -6.86%, +9.25%
Full: 3730 -> 3842 (+3.00%); split: -1.80%, +4.80%
(ss): 1877 -> 1849 (-1.49%); split: -5.59%, +4.10%
(sy): 1249 -> 1255 (+0.48%); split: -1.04%, +1.52%
(ss)-stall: 6809 -> 6364 (-6.54%); split: -13.85%, +7.31%
(sy)-stall: 17059 -> 17257 (+1.16%); split: -6.51%, +7.67%
Cat0: 17220 -> 17400 (+1.05%); split: -6.90%, +7.94%
Cat1: 5307 -> 6366 (+19.95%); split: -6.93%, +26.89%
Cat2: 39138 -> 39101 (-0.09%); split: -0.31%, +0.22%
Cat3: 16772 -> 16741 (-0.18%)
Cat5: 1269 -> 1276 (+0.55%)

I tried to pick some apps to test that looked the most impacted, and
indeed the results are mixed:

cookie_run_kingdom:         +0.275514% +/- 0.0883816% (n=68)
trex_200:                   +0.0943847% +/- 0.0297073% (n=1463)
command_and_conquer_rivals: no difference (n=131)
war_planet_online:          no difference (n=120)
lego_legacy:                -0.192131% +/- 0.152083% (n=99)
among_us:                   -0.625227% +/- 0.385419% (n=60)

Given that the perf results are small and go both ways, and apparently
we're an outlier in not always lowering mediump inputs to 16-bit, just do
it for consistency with other drivers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18506>
2022-09-14 20:42:34 +00:00
José Roberto de Souza
f4857591e1 intel/compiler/fs: Use DF to load constants when has_64bit_int is not supported
This was already been done to gen7 platforms, so now extending to all
platforms without has_64bit_int.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18577>
2022-09-14 19:32:43 +00:00
José Roberto de Souza
daf0b67bc2 intel/compiler/fs: Fix compilation of shaders with SHADER_OPCODE_SHUFFLE of float64 type
During the lower_regioning() optimization, required_exec_type() is
returning BRW_REGISTER_TYPE_UQ type when processing
SHADER_OPCODE_SHUFFLE instructions of type BRW_REGISTER_TYPE_DF but
MTL has float64 support but lacks int64 support causing shader
compilation to fail.

To fix that we could make required_exec_type() return
BRW_REGISTER_TYPE_DF in such case but SHADER_OPCODE_SHUFFLE virtual
instruction runs in the integer pipeline(inferred_exec_pipe()).

So here replacing the has_64bit check by has_64bit_int, this will
properly handle older and newer cases making this function return
BRW_REGISTER_TYPE_UD.
Then lower_exec_type() will take care to generate 2 32bits operations
to accomplish the same.

While at it also dropping the 'devinfo->verx10 == 70' check as
GFX7_FEATURES fall into the same category as MTL, has float64 but no
int64 support.

Fixes at least this crucible tests:
func.uniform-subgroup.exclusive.fadd64.q0
func.uniform-subgroup.exclusive.fmin64.q0
func.uniform-subgroup.exclusive.fmax64.q0

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18577>
2022-09-14 19:32:43 +00:00
Samuel Pitoiset
731116da1a radv: stop checking for NULL pipelines in radv_CmdBindPipeline()
This should never happen now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>
2022-09-14 19:13:43 +00:00
Samuel Pitoiset
949d76d174 radv: stop dirtying the graphics pipeline when restoring it
radv_CmdBindPipeline() does it already.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>
2022-09-14 19:13:42 +00:00
Samuel Pitoiset
73f1155193 radv: reset the compute pipeline when the saved one was NULL
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>
2022-09-14 19:13:42 +00:00
Samuel Pitoiset
3cceaaf5cd radv: do not bind NULL graphics pipeline when restoring the meta state
It's invalid to bind NULL pipelines, but make sure to reset it to
its previous NULL state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>
2022-09-14 19:13:42 +00:00
Samuel Pitoiset
9ebaa62a34 radv: stop setting redundant viewport/scissor for internal operations
Only emit them when it's needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>
2022-09-14 19:13:42 +00:00
David Riley
4031c9428f drm-shim: Allow drm-shim to work with glibc fortify.
Signed-off-by: David Riley <davidriley@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18558>
2022-09-14 18:15:44 +00:00
Boris Brezillon
e2eb1d083c ci/panvk: Skip dEQP-VK.api.object_management.max_concurrent.query_pool
This test times out occasionally. Let's disable it for now.

Reported-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18578>
2022-09-14 18:01:06 +00:00
Chad Versace
0ca7f923c5 venus: Use VkPhysicalDeviceVulkan13{Features,Properties}
Add the structs to vn_physical_device, just like we do for the 1.1 and
1.2 structs.

Prepares for Vulkan 1.3 enablement. No intended change in behavior.

Tested with gpu Intel Tigerlake on CrOS device volteer.

I tested only a small subset of dEQP because this branch only touches
the code for VkPhysicalDevice{Features2,Properties2}.

  vulkan-cts-1.3.3.0
  dEQP-VK.api.info.*
  dEQP-VK.api.smoke.*
  pass/skip/fail = 3796/9/0

I tested Dota 2 on borealis on volteer, with non-Proton Vulkan.  The
game launches and reaches the main menu. Same with Hades with DX on
Proton 7.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>
2022-09-14 15:32:22 +00:00
Chad Versace
3a366f1055 venus: Fix features/properties for unavailable extensions
In vn_physical_device_init_features() and
vn_physical_device_init_properties(), we queried many extension structs
even if the extension was unavailable. Afterwards we copied the
undefined values from the extension structs into the core structs.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>
2022-09-14 15:32:22 +00:00
Chad Versace
ca687bc263 venus: Add macros VN_SET_CORE_*
Used to refactor vn_physical_device.c.  The new code easier to read and
has less duplication.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>
2022-09-14 15:32:22 +00:00
Chad Versace
5932358447 venus: Refactor VN_ADD_TO_PNEXT
Motivation is easier sorting and readability.

- In VN_ADD_TO_PNEXT_OF, re-arrange params to allow sorting. Param1 is
  invariant in each block. Param2 is sType.

- In VN_ADD_EXT_TO_PNEXT_OF, make its initial params match those of
  VN_ADD_TO_PNEXT_OF.

- Then sort the macro calls.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>
2022-09-14 15:32:22 +00:00
Chad Versace
7c02730ed3 venus: Rename some feature/property structs
Make the variable name more closely match the type name.
This also allows them to sort correctly.

  argb_4444_formats     -> _4444_formats
  eight_bit_storage     -> _8bit_storage
  sixteen_bit_storage   -> _16bit_storage

While touching vn_physical_device.[ch], also run clang-format.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>
2022-09-14 15:32:22 +00:00
Mike Blumenkrantz
db192c0883 zink: handle split acquire/present
if the swapchain image is acquired in a different cmdbuf than it gets
presented with, the acquire semaphore will have already been submitted
by this point, and the swapchain should be flagged as such

cc: mesa-stable

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18557>
2022-09-14 15:09:44 +00:00
Mike Blumenkrantz
5505811f64 radv: avoid bottlenecking on sequential sparse buffer binds
it's more costly to submit individual sparse buffer binds than to
merge them and submit bigger binds, so try to pre-compare and flatten
out the bind array as much as possible to reduce ioctl counts

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18507>
2022-09-14 14:40:02 +00:00
Mike Blumenkrantz
054c9e708a lavapipe: ARM/EXT_rasterization_order_attachment_access
another no-op

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17956>
2022-09-14 14:19:05 +00:00