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Author SHA1 Message Date
Rob Clark
d99d358389 freedreno/ir3/ra: fix target register calculation 
Account for the # of regs an instruction writes, and fix an off-by-one.

(We are about to replace this with calculating the register target using
the live-ranges, but in debugging that it was useful to assert() if it
chose a higher target.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Rob Clark
d20a06e401 freedreno/ir3/ra: add helper to map name to instruction 
Extract out a helper from the select_reg callback.  And include all the
instructions in the hashtable, not just SFU.  This will be useful in the
following commits.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Rob Clark
29992a039e freedreno/ir3/ra: split-up 
Split out regset and shared header, since the RA pass is already getting
large-ish.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Rob Clark
6da53911c1 freedreno/ir3/ra: add debug option for RA debug msgs 
Similar to the debug switch for sched debug msgs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Rob Clark
142f2d4551 freedreno/ir3: convert debug bitfield to BITFIELD_BIT() 
(Little more verbose than the kernel's BIT())

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Rob Clark
3d0905582a freedreno/ir3: reformat disasm output 
In particular, make sure we see all the shader-db stats.  The format
(order) is the sameish, except split across multiple lines to make it
easier to read.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Rob Clark
afdb8e3907 freedreno/ir3: fix bogus register footprint with tess/gs 
When we have a tess or gs stage, VS outputs aren't normal varyings, so
regid is r63.x.. we shouldn't extend our registerfootprint to 64!

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Rob Clark
1b4b455739 freedreno/ir3: remove unused helper 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Rob Clark
c6a8792753 freedreno/ir3: add bary_ij as src for meta:tex_prefetch 
This way RA doesn't have to special case it in use/def accounting..

This gets rid of an extra level of split/collect, which shouldn't be
needed.  And interferes with scheduler trying to put tex-prefetches
after inputs but before other instructions.  (Otherwise it would have
to figure out which split/collects need to go before the tex-prefetch)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Rob Clark
a0de0db0e4 freedreno/ir3: small cleanup and comments 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Rob Clark
7d9a794f35 freedreno/a6xx: register update 
No functional change, and this register isn't used in userspace.  Just
syncing from envytools tree to eliminate the delta.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
 2020-03-27 22:41:36 +00:00
Marek Olšák
871bd2819d util: remove duplicated MALLOC_STRUCT and CALLOC_STRUCT 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
 2020-03-27 21:00:10 +00:00
Marek Olšák
7164674500 util: don't include p_defines.h and u_pointer.h from gallium 
It's a mess, but this is what I arrived at.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
 2020-03-27 21:00:10 +00:00
Marek Olšák
013b65635f radv: stop including files from mesa/main 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
 2020-03-27 21:00:10 +00:00
Marek Olšák
76f79db3f5 util: stop including files from mesa/main 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
 2020-03-27 21:00:09 +00:00
Marek Olšák
c42fa40a51 mesa: don't use <> for including internal headers 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
 2020-03-27 21:00:09 +00:00
Marek Olšák
e5339fe4a4 Move compiler.h and imports.h/c from src/mesa/main into src/util 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
 2020-03-27 21:00:09 +00:00
Jesse Natalie
6cfe074b86 wgl: use gldrv.h instead of stw_icd.h 
Now that we have the official header, let's use that instead of
stw_icd.h.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4305>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4305>
 2020-03-27 19:50:24 +00:00
Jesse Natalie
ec20169264 wgl: add official gldrv.h header-file 
This is the official, Microsoft-provided gldrv.h that describes the
driver-interface for OpenGL drivers on Windows.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4305>
 2020-03-27 19:50:24 +00:00
Karol Herbst
c9091f1f24 nv50, nvc0: fix must_check warning of util_dynarray_resize_bytes 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4330>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4330>
 2020-03-27 18:20:20 +00:00
Erik Faye-Lund
f4a4d4607e nv50: remove unused variable 
This isn't used anymore, so let's get rid of it to silence a warning.

Fixes: c574cda3c6 ("util: Make helper functions for pack/unpacking pixel rows.")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4330>
 2020-03-27 18:20:20 +00:00
Lionel Landwerlin
aad0e6f810 intel/perf: store the probed i915-perf version 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
 2020-03-27 14:14:49 +00:00
Lionel Landwerlin
8e7202d45f intel/perf: document meaning of query field 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
 2020-03-27 14:14:49 +00:00
Lionel Landwerlin
dde96d31b7 intel/perf: move mdapi query definitions to their own file 
Where they belong.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
 2020-03-27 14:14:49 +00:00
Lionel Landwerlin
33b9c7a7f6 intel/perf: break GL query stuff away 
This stuff is somewhat specific to the GL extension & drivers. On
Vulkan we won't use this, it also made a rather large file.

v2: Fix Android build (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
 2020-03-27 14:14:49 +00:00
Lionel Landwerlin
f5c5574f42 intel/perf: move register definition to special file 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
 2020-03-27 14:14:49 +00:00
Daniel Stone
bc98de4d14 util/test: Use MAX_PATH on Windows 
Windows provides MAX_PATH rather than PATH_MAX for the maximum allowable
path length. This is not a limit on the length of filename which can
exist on the filesystem, but a length on the length of path which can be
passed to Win32 API calls.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Fixes: f8f1413070 ("util/u_process: add util_get_process_exec_path")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4304>
 2020-03-27 10:32:47 +00:00
Pierre-Eric Pelloux-Prayer
8f573bdaaa util: fix process_test path 
Make sure we only use winepath when needed.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Fixes: f8f1413070 ("util/u_process: add util_get_process_exec_path")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2690
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4304>
 2020-03-27 10:32:31 +00:00
Timothy Arceri
b5e00f5c2b nir: fix packing of TCS varyings not read by the TES 
Unlike other stages TCS outputs not read by the TES cannot always
be demoted to globals e.g. when they are read by other TCS
invocations.

We were not taking these outputs into account when packing which
could result in other outputs being assigned to the same location.

Here we make sure to gather information on these outputs and group
them together when packing.

This fixes rendering issues in QUBE 2 via Proton.

Closes: #2653
Fixes: 26aa460940 ("nir: rewrite varying component packing")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
 2020-03-27 07:26:39 +00:00
Timothy Arceri
8b9ebbcb54 glsl: fix varying packing for 64bit integers 
Without this we can incorrectly end up marking things as making
use of ARB_enhanced_layouts style packing.

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
 2020-03-27 07:26:39 +00:00
Samuel Pitoiset
ba2ec1f369 ac/nir: use llvm.amdgcn.rcp in ac_build_fdiv() 
Instead of emitting 1.0 / x which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.

No pipeline-db changes with VEGA10/LLVM 9.

pipeline-db (VEGA10/LLVM 10):
Totals from affected shaders:
SGPRS: 6672 -> 6672 (0.00 %)
VGPRS: 6652 -> 6652 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 561780 -> 561692 (-0.02 %) bytes
Max Waves: 1043 -> 1043 (0.00 %)

pipeline-db (VEGA10/LLVM 11 - 92744f62478):
Totals from affected shaders:
SGPRS: 84608 -> 83768 (-0.99 %)
VGPRS: 106768 -> 106636 (-0.12 %)
Spilled SGPRs: 1625 -> 1713 (5.42 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 10850936 -> 10726712 (-1.14 %) bytes
Max Waves: 3152 -> 3180 (0.89 %)

LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.

Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
 2020-03-27 08:05:43 +01:00
Samuel Pitoiset
d548384fc6 ac/nir: use llvm.amdgcn.rsq for nir_op_frsq 
Instead of emitting 1.0 / sqrt(x) which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.

pipeline-db (VEGA10/LLVM 9):
Totals from affected shaders:
SGPRS: 16872 -> 16864 (-0.05 %)
VGPRS: 15320 -> 15464 (0.94 %)
Spilled SGPRs: 2021 -> 2133 (5.54 %)
Code Size: 1915464 -> 1917476 (0.11 %) bytes
Max Waves: 641 -> 639 (-0.31 %)

pipeline-db (VEGA10/LLVM 10):
Totals from affected shaders:
SGPRS: 43936 -> 44120 (0.42 %)
VGPRS: 41776 -> 41972 (0.47 %)
Spilled SGPRs: 875 -> 875 (0.00 %)
Code Size: 4468164 -> 4468120 (-0.00 %) bytes
Max Waves: 2412 -> 2414 (0.08 %)

pipeline-db (VEGA10/LLVM 11 - 92744f62478):
Totals from affected shaders:
SGPRS: 60096 -> 60096 (0.00 %)
VGPRS: 63552 -> 63648 (0.15 %)
Spilled SGPRs: 6135 -> 6117 (-0.29 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 6252996 -> 6249772 (-0.05 %) bytes
Max Waves: 2324 -> 2337 (0.56 %)

LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.

Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
 2020-03-27 07:45:47 +01:00
Samuel Pitoiset
66426ce119 ac/nir: use llvm.amdgcn.rcp for nir_op_frcp 
Instead of emitting 1.0 / x which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.

pipeline-db (VEG10/LLVM 9):
Totals from affected shaders:
SGPRS: 50384 -> 50312 (-0.14 %)
VGPRS: 42572 -> 42696 (0.29 %)
Spilled SGPRs: 1372 -> 1372 (0.00 %)
Code Size: 5692040 -> 5691428 (-0.01 %) bytes
Max Waves: 3954 -> 3951 (-0.08 %)

pipeline-db (VEG10/LLVM 10):
Totals from affected shaders:
SGPRS: 78512 -> 78464 (-0.06 %)
VGPRS: 62408 -> 62484 (0.12 %)
Spilled SGPRs: 1502 -> 1502 (0.00 %)
Code Size: 8106188 -> 8103372 (-0.03 %) bytes
Max Waves: 7759 -> 7753 (-0.08 %)

pipeline-db (VEGA10/LLVM 11 - 92744f62478):
Totals from affected shaders:
SGPRS: 112760 -> 113232 (0.42 %)
VGPRS: 111132 -> 110568 (-0.51 %)
Spilled SGPRs: 5870 -> 5940 (1.19 %)
Spilled VGPRs: 650 -> 652 (0.31 %)
Code Size: 11887232 -> 11561744 (-2.74 %) bytes
Max Waves: 8964 -> 9015 (0.57 %)

LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.

Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
 2020-03-27 07:45:43 +01:00
H.J. Lu
e352e7e792 x86: Add ENDBR at function entries 
Intel Control-flow Enforcement Technology (CET):

https://software.intel.com/en-us/articles/intel-sdm

contains shadow stack (SHSTK) and indirect branch tracking (IBT).
When IBT is enabled, all indirect branch targets must start with
ENDBR instruction which is a NOP on non-CET processors.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2538

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3865>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3865>
 2020-03-26 16:38:46 -07:00
Marek Olšák
9899a8e26c mesa: try to fix the android build 
Fixes: 8a3e2cd9b2
Closes: #2685

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4325>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4325>
 2020-03-26 18:43:42 -04:00
Francisco Jerez
36c155a017 intel/fs/gen12: Fix interaction of SWSB dependency combination with EU fusion workaround. 
This has been reported to fix a hang in Shadow of Mordor on Gen12.
One of its compute shaders seems to cause an in-order exec_all
dependency to be merged into an out-of-order SET dependency slot,
which would prevent us from baking the SET dependency into the parent
instruction, leading to an assert failure in emit_inst_dependencies()
(Thanks to Rafael for noticing that).  Prevent that by avoiding
combination of in-order dependencies whenever that would cause a SET
dependency to be demoted to a SYNC.NOP instruction.

Fixes: e14529ff32 "intel/fs/gen12: Workaround data coherency issues due to broken NoMask control flow."
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
 2020-03-26 19:09:42 +00:00
H.J. Lu
007e623025 x86_init_func_common: Add ENDBR at function entry 
Intel Control-flow Enforcement Technology (CET):

https://software.intel.com/en-us/articles/intel-sdm

when IBT is enabled, all indirect branch targets must start with ENDBR
instruction which is a NOP on non-CET processors.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2575

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3985>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3985>
 2020-03-26 18:36:20 +00:00
Danylo Piliaiev
2d0599b1b4 intel/aub_viewer: Fix format specifier for uint64_t 
Use PRIx64 instead of lx for uint64_t

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2692
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4331>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4331>
 2020-03-26 18:00:15 +00:00
Icecream95
7b9f1b6ef7 panfrost: Extend the tiled store fast-path to loads 
The access functions are forced to be inline, so performance shouldn't
be impacted for stores.

WebGL performance in Firefox is more than doubled, and track loading
in STK is noticeably faster.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4317>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4317>
 2020-03-26 14:34:55 +00:00
Icecream95
dac1573a35 mesa/format_utils: Add a fast-path for RGBA to BGRA 
This is similar to an existing fast-path, but this is for an array
source while the existing one is for an array destination.

Firefox can hit this case for WebGL when GL compositing is not used.
For a WebGL sample on the Panfrost driver, the frame-rate increased
from 19.4 fps to 20.6 fps, which is a 6% gain.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4315>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4315>
 2020-03-26 13:36:47 +00:00
Tapani Pälli
0847fe6e7f glsl: set error_emitted true if type not ok for assignment 
Patch changes also existing assert to not trigger when we have
error types in assignment.

v2: simplify, cleanup (Ian)

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2629
Fixes: d1fa69ed61 ("glsl: do not attempt assignment if operand type not parsed correctly")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4178>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4178>
 2020-03-26 12:41:12 +00:00
Boris Brezillon
efdce97e4b vtn/opencl: add rint-support 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
 2020-03-26 10:14:22 +00:00
Erik Faye-Lund
6d69ed88f8 vtn/opencl: add native exp2/log2-support 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
 2020-03-26 10:14:22 +00:00
Erik Faye-Lund
7b2bfb6bc4 vtn/opencl: add native exp10/log10-support 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
 2020-03-26 10:14:22 +00:00
Erik Faye-Lund
25cb87bcdd vtn/opencl: add native exp/log-support 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
 2020-03-26 10:14:22 +00:00
Erik Faye-Lund
c98e745e78 compiler/nir: move build_log helper into builtin-builder 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
 2020-03-26 10:14:22 +00:00
Erik Faye-Lund
f59ae68838 compiler/nir: move build_exp helper into builtin-builder 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
 2020-03-26 10:14:22 +00:00
Erik Faye-Lund
4821ec6d8f vtn/opencl: fully enable OpenCLstd_Clz 
Fixes: 7325f6ac98 ("vtn/opencl: add clz support")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
 2020-03-26 10:14:22 +00:00
Marek Olšák
b94c277fd1 radeonsi: enable full out-of-order drawing when allow_draw_out_of_order is set 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
 2020-03-26 03:08:34 -04:00
Marek Olšák
8c053e5fad mesa: allow out-of-order drawing to optimize immediate mode if it's safe 
This increases performance by 11-13% in Viewperf11/Catia - first scene.

Set allow_draw_out_of_order=true to enable this.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
 2020-03-26 03:08:34 -04:00