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freedreno/ir3/ra: add debug option for RA debug msgs

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Similar to the debug switch for sched debug msgs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
This commit is contained in:
Rob Clark 2020-03-23 08:58:07 -07:00 • committed by Marge Bot
parent 142f2d4551
commit 6da53911c1
3 changed files with 39 additions and 18 deletions
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8
src/freedreno/ir3/ir3_compiler.c
View file

@ -39,10 +39,12 @@ static const struct debug_named_value shader_debug_options[] = {
{"optmsgs", IR3_DBG_OPTMSGS, "Enable optimizer debug messages"},
{"forces2en", IR3_DBG_FORCES2EN, "Force s2en mode for tex sampler instructions"},
{"nouboopt", IR3_DBG_NOUBOOPT, "Disable lowering UBO to uniform"},
#ifdef DEBUG
{"schedmsgs", IR3_DBG_SCHEDMSGS, "Enable scheduler debug messages"},
#endif
{"nofp16", IR3_DBG_NOFP16, "Don't lower mediump to fp16"},
#ifdef DEBUG
/* DEBUG-only options: */
{"schedmsgs", IR3_DBG_SCHEDMSGS, "Enable scheduler debug messages"},
{"ramsgs", IR3_DBG_RAMSGS, "Enable register-allocation debug messages"},
#endif
DEBUG_NAMED_VALUE_END
};

7
src/freedreno/ir3/ir3_compiler.h
View file

@ -92,8 +92,11 @@ enum ir3_shader_debug {
IR3_DBG_OPTMSGS = BITFIELD_BIT(7),
IR3_DBG_FORCES2EN = BITFIELD_BIT(8),
IR3_DBG_NOUBOOPT = BITFIELD_BIT(9),
IR3_DBG_SCHEDMSGS = BITFIELD_BIT(10),
IR3_DBG_NOFP16 = BITFIELD_BIT(11),
IR3_DBG_NOFP16 = BITFIELD_BIT(10),
/* DEBUG-only options: */
IR3_DBG_SCHEDMSGS = BITFIELD_BIT(20),
IR3_DBG_RAMSGS = BITFIELD_BIT(21),
};
extern enum ir3_shader_debug ir3_shader_debug;

42
src/freedreno/ir3/ir3_ra.c
View file

@ -32,6 +32,21 @@
#include "ir3.h"
#include "ir3_compiler.h"
#ifdef DEBUG
#define RA_DEBUG (ir3_shader_debug & IR3_DBG_RAMSGS)
#else
#define RA_DEBUG 0
#endif
#define d(fmt, ...) do { if (RA_DEBUG) { \
printf("RA: "fmt"\n", ##__VA_ARGS__); \
} } while (0)
#define di(instr, fmt, ...) do { if (RA_DEBUG) { \
printf("RA: "fmt": ", ##__VA_ARGS__); \
ir3_print_instr(instr); \
} } while (0)
/*
* Register Assignment:
*
@ -1097,7 +1112,7 @@ static void
print_bitset(const char *name, BITSET_WORD *bs, unsigned cnt)
{
bool first = true;
debug_printf(" %s:", name);
debug_printf("RA: %s:", name);
for (unsigned i = 0; i < cnt; i++) {
if (BITSET_TEST(bs, i)) {
if (!first)
@ -1131,34 +1146,35 @@ ra_add_interference(struct ir3_ra_ctx *ctx)
/* update per-block livein/liveout: */
while (ra_compute_livein_liveout(ctx)) {}
if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
debug_printf("AFTER LIVEIN/OUT:\n");
if (RA_DEBUG) {
d("AFTER LIVEIN/OUT:");
foreach_block (block, &ir->block_list) {
struct ir3_ra_block_data *bd = block->data;
debug_printf("block%u:\n", block_id(block));
d("block%u:", block_id(block));
print_bitset(" def", bd->def, ctx->alloc_count);
print_bitset(" use", bd->use, ctx->alloc_count);
print_bitset(" l/i", bd->livein, ctx->alloc_count);
print_bitset(" l/o", bd->liveout, ctx->alloc_count);
}
foreach_array (arr, &ir->array_list) {
debug_printf("array%u:\n", arr->id);
debug_printf(" length: %u\n", arr->length);
debug_printf(" start_ip: %u\n", arr->start_ip);
debug_printf(" end_ip: %u\n", arr->end_ip);
d("array%u:", arr->id);
d(" length: %u", arr->length);
d(" start_ip: %u", arr->start_ip);
d(" end_ip: %u", arr->end_ip);
}
debug_printf("INSTRUCTION VREG NAMES:\n");
d("INSTRUCTION VREG NAMES:");
foreach_block (block, &ctx->ir->block_list) {
foreach_instr (instr, &block->instr_list) {
if (!ctx->instrd[instr->ip].defn)
continue;
debug_printf("%04u: ", scalar_name(ctx, instr, 0));
ir3_print_instr(instr);
if (!writes_gpr(instr))
continue;
di(instr, "%04u", scalar_name(ctx, instr, 0));
}
}
debug_printf("ARRAY VREG NAMES:\n");
d("ARRAY VREG NAMES:");
foreach_array (arr, &ctx->ir->array_list) {
debug_printf("%04u: arr%u\n", arr->base, arr->id);
d("%04u: arr%u", arr->base, arr->id);
}
}