Commit graph

212589 commits

Author SHA1 Message Date
swscm, z1
d79665066d amd/vpelib: Ensures type-safe comparison for callback assignment
[WHY & How]
Ensures type-safe comparison for the sys_event callback assignment by
casting the NULL constant to the appropriate function pointer type.

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Muhammad Ansari <Muhammad.Ansari@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37504>
2025-09-22 10:37:21 +00:00
Zhao, Jiali
237ab0778e amd/vpelib: Create Function to Check for Blending Feature
[HOW]
Created check_blending_support function and condition to check for
readable purpose

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Zhao, Jiali <Jiali.Zhao@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37504>
2025-09-22 10:37:21 +00:00
Karol Herbst
6f41c62720 rusticl/mesa: make PipeScreen refcounted
Reviewed-by: Seán de Búrca <sdeburca@fastmail.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37377>
2025-09-22 10:16:13 +00:00
Karol Herbst
501f59e159 rusticl/mesa: make PipeScreen transparent
Reviewed-by: Seán de Búrca <sdeburca@fastmail.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37377>
2025-09-22 10:16:13 +00:00
Karol Herbst
f7fcd7ed5d rusticl/mesa: rework Context creation
Reviewed-by: Seán de Búrca <sdeburca@fastmail.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37377>
2025-09-22 10:16:12 +00:00
Karol Herbst
6a71ecaad7 rusticl/mesa: add PipeScreen::pipe
Reviewed-by: Seán de Búrca <sdeburca@fastmail.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37377>
2025-09-22 10:16:11 +00:00
Karol Herbst
b67be5d829 rusticl/util: make ThreadSafeCPtr Copy, Clone and transparent
Reviewed-by: Seán de Búrca <sdeburca@fastmail.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37377>
2025-09-22 10:16:11 +00:00
Qiang Yu
d52452a486 glsl: allow barrier builtin functions for mesh shader
Some checks are pending
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Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:50 +00:00
Qiang Yu
9ffbf9f96b glsl: translate mesa stage for mesh shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:50 +00:00
Qiang Yu
ecb1322737 glsl: flat qualifier is not needed for per primitive IO
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:50 +00:00
Qiang Yu
521aa2e010 glsl: no xfb buffer qualifier for mesh shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:50 +00:00
Qiang Yu
8c58bd5acf glsl: lower shared and task playload for mesh shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:49 +00:00
Qiang Yu
2b76809dfc glsl: handle explicit location for mesh shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:49 +00:00
Qiang Yu
bd365d1d2a glsl: handle mesh shader when optimize varying
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:49 +00:00
Qiang Yu
6176b85d2c glsl: add mesh pipeline varying linkage
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:48 +00:00
Qiang Yu
6e41854f1d glsl: pack varying limit check code into functions
To be shared with mesh shader linkage.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:48 +00:00
Qiang Yu
59f1186af2 glsl: pack vertex pipeline varying linkage into a function
No functional change, prepare for add mesh pipeline varying
linking.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:48 +00:00
Qiang Yu
c6b24b4cc2 glsl: disable mesh shader output remove when separate shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:47 +00:00
Qiang Yu
38d385673f glsl: validate MS/FS interstage in/out variable type
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:46 +00:00
Qiang Yu
6da726c59c glsl: handle per primitive varying when link
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:46 +00:00
Qiang Yu
faa9fea7d2 glsl: validate MS/FS interstage in/out block
Mesh shader output block is always in array type, need
to validate if the mesh shader output array element type
match the fragment shader input type.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:45 +00:00
Qiang Yu
ae3c0ac9e9 glsl: gl_nir_link_glsl handle mesh shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:45 +00:00
Qiang Yu
5b87ef9560 glsl: nir_build_program_resource_list support mesh shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:44 +00:00
Qiang Yu
30fde159eb glsl: add mesh shader builtin functions
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:44 +00:00
Qiang Yu
69127db647 glsl: handle mesh shader output block
Mainly redeclare of gl_MeshPerVertexEXT and gl_MeshPerPrimitiveEXT.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:43 +00:00
Qiang Yu
0e26c48d79 glsl: assign mesh shader output variable array size
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:42 +00:00
Qiang Yu
6a2bf2024d glsl: add mesh shader builtin outputs
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:42 +00:00
Qiang Yu
c260aa3928 glsl: add input builtin variables for mesh shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:42 +00:00
Qiang Yu
691601e89e glsl: handle work group in layout for mesh shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:41 +00:00
Qiang Yu
611370965f glsl: handle max_vertices/primitives for mesh shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:40 +00:00
Qiang Yu
de22e59231 glsl: handle mesh shader primitive type layout qualifier
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:39 +00:00
Qiang Yu
c2a35ae70d glsl: allow shared variables in task and mesh shader
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:38 +00:00
Qiang Yu
6415cec230 glsl: handle PerPrimitiveEXT qualifier
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:37 +00:00
Qiang Yu
b2e9a6d935 glsl: handle taskPayloadSharedEXT variables
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:36 +00:00
Qiang Yu
2b8c273322 glsl: prepare parse state for mesh shader
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36405>
2025-09-22 02:19:35 +00:00
Qiang Yu
93024ea247 radeonsi: hide real modifier export behind AMD_DEBUG
Some checks are pending
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Some applications are not ready to handle multi plane
modifiers.

User who want this feature can use AMD_DEBUG=export_modifier
to enable it again.

Fixes: 0a266f0256 ("radeonsi: really support eglExportDMABUFImageQueryMESA")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13917
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37433>
2025-09-22 01:51:21 +00:00
Qiang Yu
996c0af482 radeonsi: fix use aco/llvm debug options
They should be moved to shader options.

Fixes: 5c92fe45a1 ("radeonsi: support more than 64 options for AMD_DEBUG")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37433>
2025-09-22 01:51:21 +00:00
Rob Clark
3a4b3322d4 freedreno/decode: checkreg handling for bitsize/stride
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The initial version was not accounting for reg64 vs reg32, or array
stride.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37502>
2025-09-21 08:27:00 -07:00
Rob Clark
159d0596c4 freedreno/registers: Fix x_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE
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The HLSQ version only existed in a6xx.  And the SP one had the wrong
offset.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37484>
2025-09-20 16:52:22 +00:00
Rob Clark
897a47602a freedreno/registers: Remove conflicting RBBM regs
These are the same as a6xx, so just keep the declarations without
variants attribute.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37484>
2025-09-20 16:52:21 +00:00
Rob Clark
68e5f150e3 freedreno/decode: Add test to check for conflicting regs
Add a tool to check for conflicting/overlapping register definitions.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37484>
2025-09-20 16:52:21 +00:00
stefan11111
8e000cecac glx: Fix segfault when Nvidia PRIME render offload is enabled, but not used
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Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11719

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37342>
2025-09-20 08:43:00 +00:00
Eric Engestrom
19dc279d43 zink/ci: drop gbm override now that debian has a usable xorg
Some checks are pending
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https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35853 gave us
a debian package which has `--disable-thread-safety-constructor` removed,
fixing this bug.

The `blender-demo-ellie_pose.trace` and `counterstrike-v2.trace` updates
are because there's a rectangle at the top (for blender, window title
bar I expect) or on the sides (counterstrike, padding for image ratio)
which renders grey in gbm and black in xorg.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37437>
2025-09-20 06:59:01 +00:00
Roland Scheidegger
b0be900f93 llvmpipe: implement GL_ARB_sample_locations
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Needing the positions both in the scene for rasterization (in fixed point)
and in the fs (as floats) is a bit awkward, for now just put it in fs key.
Otherwise pretty straight forward.

Reviewed-by: Michal Krol <michal.krol@broadcom.com>
Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37181>
2025-09-20 01:57:05 +00:00
Roland Scheidegger
60924b4819 gallium,mesa/st: reverse logic for y flip for programmable sample locations
mesa/st flips y coordinates if fbo orientation is Y_0_BOTTOM (essentially
user fbos), and all 3 gallium drivers supporting the feature then
unconditionally reverse this flip. llvmpipe wants to support this as well,
and it would have to do the flip too, and it's actually problematic for
lavapipe, since then lavapipe would have to flip as well, which means that
we'd lose the ability to set y positions to 0 (as the flip with the 4 bit
values does 16-val), and vulkan requires the minimum to be 0.
Hence, reverse this and flip when fbo orientation is Y_0_TOP. I don't actually
pretend to know if this is correct or if just no flipping should occur, but at
least this is consistent with how default sample locations are reported by mesa
via glGetMultisamplefv (which does y flip with the values it gets via
pipe->get_sample_position() if it's a winsys fb).

Reviewed-by: Michal Krol <michal.krol@broadcom.com>
Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37181>
2025-09-20 01:57:04 +00:00
Roland Scheidegger
c3cf50e2f1 lavapipe: expose support for msaa 8x
There's nothing to be done in lavapipe, all handled by llvmpipe.

There's a couple new failures in zink with 6/8 samples, but they are all the
same as already happening with 2/4 samples, so nothing specific to 8 samples.

Reviewed-by: Michal Krol <michal.krol@broadcom.com>
Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37181>
2025-09-20 01:57:04 +00:00
Roland Scheidegger
92550b106c llvmpipe: fix incorrect scissor planes
The scissor planes we were setting up did not actually correspond to scissor
with widths / heights being a multiple of full pixels, rather they had an
excess width / height of (nearly) half a pixel (at the x0 and y0 edges).
(Note it's not an actual scissor as in graphics APIs terms, it's the
intersection of fb/viewport/scissor.)
Without multisampling that was still fine (since we always test at pixel
center) however vk cts complained (for some reason only when using 8 samples
(not announced by lavapipe yet) - no idea why it doesn't fail when using 4
samples), in tests such as
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_8.s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,
which uses scissor and noted that the result for some pixels which are outside
the rendering area don't contain the clear color. And actually a llvmpipe
test was failing as well.

There is in fact no need for separate adjustments for msaa at all, as long
as we ensure that x0, y0, x1, y1 all are exactly on their respective plane
edges (inclusive for x0/y0, exclusive for x1/y1). So the logic is mostly
reverted to what it was before this was adjusted for msaa (albeit the original
code then had an excess adjustment of nearly a full pixel at the x0 and y0
edges which is probably why it didn't work for msaa).

Fixes a couple cases of clip-and-scissor-blit tests in llvmpipe and various
other drivers hitting this indirectly. Interestingly though not quite all cases
are fixed and even more odd is that not exactly the same cases are fixed for
all drivers, so maybe there's more to it (need to respect bottom_edge_rule or
something similar?)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37181>
2025-09-20 01:57:04 +00:00
Roland Scheidegger
404cbc28d9 lavapipe: don't leak the temporary msaa resource
The temporary resource created for render_to_single_sampled was never freed,
hence asan complaining.
Let's fix this before announcing support for msaa 8x in lavapipe, which
otehrwise causes more failures there.
(As a side note, no matter what I try I can't get asan complaining about
this locally, so just relying on ci here.)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37181>
2025-09-20 01:57:03 +00:00
Roland Scheidegger
762fd255d8 docs: fix up old comment about fake msaa for llvmpipe
llvmpipe has supported real msaa for quite some time.

Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Reviewed-by: Michal Krol <michal.krol@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37181>
2025-09-20 01:57:03 +00:00
Roland Scheidegger
0064baeaa5 llvmpipe: add bitcasts around fptrunc/fpext operations
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We are using different llvm type depending on the cpu supporting f16c
instructions or not.
The reasoning behind this was that we really couldn't do anything with f16
values and had to cast them to some int type anyway, plus IIRC originally
this actually predates llvm even supporting a half type in the first place
(or if it did, at the very least it was not able to do anything useful with
it).
There are now bugs with lavapipe when the cpu doesn't support f16c, since while
we don't expose f16 capabilities in this case, we can still hit f16 conversion
functions for the likes of unpack2x16float and quantizeToF16, and we're just
straight calling fpext/fptrunc functions, not touching our own code for half
conversion (I believe our own code might still be faster as llvm de-vectorizes
it if it's not supported by the cpu, but don't quote me on that - could depend
on llvm version, and also for trunc the rounding is actually different since
our own functions implement rounding according to d3d10 requirements (mostly
used for f16 render targets)).
This only seems to be a problem for vulkan, not GL, since glsl has its own
lowering pass if the half float packing instructions aren't supported by the
driver.
Ideally we'd fix this by just always using llvm half type for f16, however
still not all llvm backends can handle it.
So instead do some hacky bitcasts around the fpext/fptrunc calls with f16,
which works on x86 even when not supporting f16c. Other llvm backends not
really supporting halfs will still crash there as before (albeit it should
be a "cleaner" crash as the IR is now correct...), but at least keeps them
running for more ordinary things such as f16 texture sampling / render
targets (which they wouldn't if we'd use llvm half type everywhere).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13807
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13865
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37344>
2025-09-20 01:32:46 +00:00