anv_state::offset in the context of anv_state_pool is equal to the offset from
the begining of block_pool + start_offset.
Like it is set in anv_state_pool_alloc_no_vg() in the path that allocs a new
block in anv_block_pool.
As anv_state_pool_return_chunk() expects only the offset from the begining of
anv_block_pool so here subtracting to make the path that grabs a larger chunk of
memory of the pool and split into smaler chunks to properly work.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37669>
Only 3 pools sets a value different than zero to start_offset so that might be
a issue that was being hidden by luck.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37669>
struct anv_state::offset and struct anv_block_pool::max_size are 64bits so these
parameters should also be 64bit or risk overflow.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37669>
While at it also renaming EMPTY to ANV_FREE_LIST_EMPTY_VAL to be more explicit.
No changes in behavior expected here.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37669>
We currently pass the NIR field directly from the iris_uncompiled_shader
struct, which works in most cases, however, in the caes where we create
a passthrough TSC shader, the uncompiled shader is nullptr, which would
create a null dereference. Instead, pass the NIR shader directly to the
function, so we can pass the passthrough shader.
CID: 1666496
Fixes: dedbe0e826 ("iris: Create archive file when using INTEL_DEBUG=mda")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37751>
Although this isn't technically required by the Vulkan spec, a few
native Vulkan games including DOOM Eternal expect it to be supported
because Windows drivers all support it. Now that support has been
plumbed through in the kernel backend, expose the ability to submit
sparse binds on the graphics queue that are implicitly synchronized with
graphics commands.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37304>
Create an extra sparse queue when creating a graphics queue, and send
sparse binds to that queue. Synchronize graphics commands against sparse
binds and vice versa using a pair of timeline semaphores.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37304>
Vulkan 1.0 conformance has happened on BXS-4-64, but not on other GPUs
or Vulkan versions using an upstream version of the driver. So let's
update the phrasing to include this.
And since we actually expose Vulkan 1.2 now (see next commit), let's
untangle the conformance information from the GPUs support table; this
way nobody should be confused and think we're conformant to Vulkan 1.2,
when we're not (yet).
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37678>
This driver landed after the move to ld_args_build_id, so it never got
converted over. Let's make sure it's testing for the feature support
rather than just assuming it's there.
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37393>
This also includes support for the new job cookie system, verifying that jobs
running originate from the claimed source. This is useful internally but won't
affect users, unlike the feature in the title :)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37609>
All the compiler support was implemented as part of the v3dv
implementation (see commit 31e8740808 and MR#27211).
We are using the same size/supported_stages and mostly the same
supported features, so probably at some point it would be good to have
a common place for that info. Zink reuses their definitions, but as
far as I see it does that because the PIPE and equivalent VK
definitions has the same values, that seems somewhat fragile.
We don't support all features, and in order to support arithmetic we
need to enable a lowering.
Using CTS, right now we are passing 1023 tests out of 6053 (the rest
are skipped).
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37621>
The kernel driver zero initialises device memory allocations for us, so all that
needs to be done is to advertise support for the extension.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37732>
In general, the debug flags are served once per proc invocation. So we
can make panvk debug flags global and clean up the existing codes in the
next change. Meanwhile, this changes improves branch prediction on user
builds and logs the enabled debug options when startup is used.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37752>
Fix defect reported by Coverity Scan.
Evaluation order violation (EVALUATION_ORDER)
write_write_typo:
In ret = ret = ({...; drmIoctl(panfrost_device_fd(dev), 3221775434UL, &args);}),
ret is written twice with the same value.
Fixes: e9aedfe508 ("panfrost: Support JM context creation and destruction")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37708>
These registers are shared between BR and BV. This means they can only
be written in BV or in BR during a special "disable binning" section
which synchronizes BR and BV. The register stomping infrastructure isn't
aware of this, so disable stomping for VSC.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37722>
