Commit graph

181834 commits

Author SHA1 Message Date
Samuel Pitoiset
d686ba36a9 radv/amdgpu: simplify cs_execute_ib()
It's only used for executing IB2 on GFX.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30809>
2024-10-10 14:08:39 +00:00
Samuel Pitoiset
c1b2cb6ef7 radv: implement IB chaining for DGC when it's executed on compute
The IB2 packet is only supported on the graphics queue. To execute DGC
IB on compute, the previous solution was to submit it separately
without any chaining. Though this solution was incomplete because it's
easy to reach the maximum number of IBs per submit when there is a lot
of ExecuteIndirect() calls.

To fix that, the proposed solution is to implement DGC IB chaining when
it's executed on the compute only. The idea is to add a trailer that is
added at the beginning of the DGC IB (to know the offset). This trailer
is used to chain back back the DGC IB to a normal CS, it's patched at
execution time. Patching is fine because it's not allowed to execute
the same DGC IB concurrently and the entire solution relies on that.

When the DGC IB is executed on graphics, the trailer isn't patched and
it only contains NOPs padding. Performance should be mostly similar.

This fixes
dEQP-VK.dgc.nv.compute.misc.execute_many_*_primary_cmd_compute_queue.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30809>
2024-10-10 14:08:39 +00:00
Samuel Pitoiset
303a456aa5 radv: add PKT3_INDIRECT_BUFFER_BYTES in the DGC path
To avoid using a magic number.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30809>
2024-10-10 14:08:39 +00:00
Samuel Pitoiset
056b638588 radv: add a helper to bind the color output state
Instead of duplicating almost the same code chunk in three different
locations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31566>
2024-10-10 13:19:22 +00:00
Samuel Pitoiset
39745dd7cf radv: move radv_compact_spi_shader_col_format() to radv_cmd_buffer.c
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31566>
2024-10-10 13:19:22 +00:00
Zan Dobersek
61ad069a21 freedreno: sanitize device names for config name usage
Names used in libconfig's configuration files only allow alphanumerics,
underscores, dashes and asterisks. Freedreno device names, used as names
in fdperf.cfg, can also contain other characters, currently spaces and
plus characters. Not accounting for those makes it impossible to store
fdperf configuration across separate runs.

Once the Freedreno device name is retrieved, it's now sanitized for use
in fdperf.cfg. Unsupported characters are converted to underscores.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31577>
2024-10-10 11:48:45 +00:00
Daniel Stone
3e7c9aad8a ci/virgl: Fix library path
We need to set $LD_LIBRARY_PATH so we can find GL/Vulkan at all, and
$LIBGL_DRIVERS_PATH so Xvfb will pick up the correct DRI modules.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Daniel Stone
4e3e84c240 ci/zink: Fix library path
We need to set $LD_LIBRARY_PATH so we can find GL at all, and
$LIBGL_DRIVERS_PATH so Xvfb will pick up the correct DRI modules.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Daniel Stone
61f5178f6e ci/swrast: Archive Xvfb logs
If anything goes wrong, it's useful to have actual output, as opposed to
guessing from the void.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Daniel Stone
8b594d29b6 ci/swrast: Fix library paths for llvmpipe/softpipe
We need to set $LIBGL_DRIVERS_PATH so Xvfb will pick up the correct DRI
modules. We were setting $LD_LIBRARY_PATH, but llvmpipe was getting it
wrong, so Weston was picking up the host GLES, which we're about to no
longer install.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Tapani Pälli
e4fcbe8d6f anv: set StackIDControlOverride_RTGlobals for 2 workarounds
GFX_VER block matches both workarounds and while these workarounds are
almost about the same cause, other one applies only for LNL and other
one for BMG, need to check for both.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31571>
2024-10-10 10:20:56 +00:00
Tapani Pälli
b8fc0288af intel/dev: update mesa_defs.json from workaround database
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31571>
2024-10-10 10:20:56 +00:00
Erik Faye-Lund
aa517f7eb3 mesa: clean up setup of MaxAddressRegs constant
This value is only ever read for vertex or fragment shaders, so let's
make sure it's zero otherwise.

While we're at it, make the state-tracker not overwrite MaxAddressRegs
to the same value as it already is.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31538>
2024-10-10 09:36:43 +00:00
Erik Faye-Lund
12eba85544 mesa: remove superfluous "native" limits and stats
We don't ever set these to anything else than the same as the non-native
counterparts. Let's drop the members in the first place, and use the
non-native version instead.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31538>
2024-10-10 09:36:43 +00:00
Erik Faye-Lund
cf71e5534b i915: do not calculate native instructions
This isn't wired up anywhere, so let's just drop it.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31538>
2024-10-10 09:36:43 +00:00
David Rosca
3c5fe03b92 radeonsi/vcn: Add support for VCN5 dpb tier2
Co-authored-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
1e1f078099 radeonsi/vcn: Add support for VCN5 AV1 compound
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
05f7589fec radeonsi/vcn: Fix coded size in sequence header on VCN5
Introduce coded_width/coded_height for values used in headers
and change it to aligned size on VCN4 to reflect the actual coded size.
VCN5 doesn't have this limitation and can code any size.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
8b2f0fb574 radeonsi/vcn: Support raw packed headers for AV1
Same as H264/HEVC, we still write sequence header ourselves
and slice header is sent to FW, everything else gets copied
directly to output bitstream buffer.
Fixes generating correct output with libva-utils/av1encode.
Also fixes temporal delimiter insertion, it's no longer forced
on every frame, but instead it lets application handle it.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
46d8e57f16 frontends/va: Remove now unused ref fields for AV1 encode
Need to get rid of these as they allocate buffers for drivers
not implementing create_dpb_buffer and waste memory.
No driver is using these fields anymore.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
David Rosca
813812b925 radeonsi/vcn: Switch to app DPB management for AV1
Also move the common part of the frame header into shared function.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
David Rosca
454a26662d frontends/va: Support raw packed headers for AV1
When there is show_existing_frame = 1 frame header, we don't parse
it and instead output directly as raw header. Only the frame header
that will be used for encoding current frame is parsed and indicated
with is_slice.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
David Rosca
1fdd773450 frontends/va: Parse more AV1 frame and sequence header params
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
David Rosca
36ddcc130b frontends/va: Implement DPB management for AV1
Same logic as H264 and HEVC, except surfaces are evicted immediately.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
Christian Gmeiner
3ae3425c5d etnaviv: blt: Convert assert to real if
etna_try_blt_blit(..) returns if it is possible to do the blit
in hardware or not. When building mesa in debug mode this assert(..)
is hit many times.

Fixes the following piglits on GC7000L:
 - spec@!opengl 1.0@gl-1.0-scissor-copypixels
 - spec@nv_conditional_render@copypixels
 - spec@!opengl 1.1@copypixels-draw-sync
 - spec@!opengl 1.1@copypixels-sync
 - spec@!opengl 1.1@depthstencil-default_fb-blit
 - spec@!opengl 1.1@draw-copypixels-sync
 - spec@!opengl 1.1@gl-1.1-xor-copypixels

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31581>
2024-10-10 08:31:53 +00:00
Iago Toral Quiroga
4d1971f17f broadcom: fix pairing tmu lookup with previous ldtmu
There are some restrictions when pairing a new TMU lookup with
a previous LDTMU and we had code to handle this but we were not
limiting the restriction only to TMU lookups.

total instructions in shared programs: 10856992 -> 10823967 (-0.30%)
instructions in affected programs: 1823670 -> 1790645 (-1.81%)
helped: 10212
HURT: 110
Instructions are helped.

total max-temps in shared programs: 2234069 -> 2233153 (-0.04%)
max-temps in affected programs: 15100 -> 14184 (-6.07%)
helped: 660
HURT: 3
Max-temps are helped.

total sfu-stalls in shared programs: 15935 -> 15967 (0.20%)
sfu-stalls in affected programs: 317 -> 349 (10.09%)
helped: 31
HURT: 57
Inconclusive result (%-change mean confidence interval includes 0).

total inst-and-stalls in shared programs: 10872927 -> 10839934 (-0.30%)
inst-and-stalls in affected programs: 1824656 -> 1791663 (-1.81%)
helped: 10199
HURT: 111
Inst-and-stalls are helped.

total nops in shared programs: 185612 -> 185767 (0.08%)
nops in affected programs: 4865 -> 5020 (3.19%)
helped: 164
HURT: 256
Nops are HURT.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31574>
2024-10-10 06:58:15 +00:00
David Rosca
20d5020ad7 radeonsi/vcn: Fix out of bounds read in H264 decode
When all 16 references are used, this would read pic->ref[16].
Same for HEVC, but HEVC only uses 15 reference frames so it would
never happen there yet is still reported by coverity.

Fixes coverity issues 1497283 and 1465569 Out-of-bounds read

Cc: mesa-stable

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
2024-10-10 06:25:36 +00:00
David Rosca
10a7356488 radeonsi/vcn: Fix out of bounds write when invalidating QP map regions
Fixes coverity issue 1559460 Out-of-bounds write

Fixes: 9c07a2e10d ("radeonsi/vcn: ROI feature implementation")

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
2024-10-10 06:25:35 +00:00
David Rosca
17842f0584 radeonsi/vcn: Fix some small coverity issues
* 1619409 Resource leak
  - fix leak when mapping encode bitstream buffer fails
* 1619403 Dereference after null check
  - remove size ptr NULL check in radeon_enc_get_feedback, can't be NULL
* 1434887 Out-of-bounds access
  - use correct variable for memset in get_vp9_msg
* 1619400 'Constant' variable guards dead code
  - remove code handling frame_mbs_only_flag == 0, hardcoded to true

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
2024-10-10 06:25:35 +00:00
Tapani Pälli
f77ffd6b7c drirc/anv: force_vk_vendor=-1 for Silent Hill 2
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11992
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31573>
2024-10-10 04:07:12 +00:00
Caio Oliveira
c06a55fd39 spirv: Update SPIR-V grammar to use aliases
For enumerants and instruction names, instead of duplicating the values
now the grammar will use an aliases field to list the alternative names.
Update the Python scripts for that.

The new SPIR-V files correspond to d92cf88c371424591115a87499009dfad41b669c
("Add "aliases" fields to the grammar and remove duplicated (#447)")
in https://github.com/KhronosGroup/SPIRV-Headers.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31369>
2024-10-10 02:48:00 +00:00
Guilherme Gallo
59d909eb56 ci/lava: Make perf jobs use pyutils artifact
Following the merge of Merge Request #31151, we encountered an issue
where the performance jobs were failing silently. Although these
failures did not cause the pipeline to fail, they resulted in warnings
for all merge requests that ran the .*-traces-performance jobs, putting
critical performance data for the [Mesa Performance Driver
dashboard](https://ci-stats-grafana.freedesktop.org/goto/G3xkvykHg?orgId=1)
at risk.

To resolve this issue, this commit updates the LAVA performance jobs to
utilize the Pyutils artifact package, which is now the only required
artifact for the jobs that run the LAVA job submitter.

Fixes: dd5d737e6c ("ci/lava: Use new pyutils container")

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31553>
2024-10-10 01:33:16 +00:00
Rob Clark
f54748ea38 freedreno/drm: Add preemption support
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
753c8bf834 freedreno/a6xx: Emit CP_SET_AMBLE packets
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
d572fcf04a freedreno/a6xx: Move more state emit per-bin
With skipsaverestore=1 we can't rely on this values being restored.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
270e595811 freedreno/a6xx: Move static regs to preamble IB
We can re-use this for preemption.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
0c36ca7446 freedreno/a6xx: Move PC_TESSFACTOR_ADDR emit
This depends on batch state, so emit in gmem code.  The remainder of the
static reg initialization can be re-used across batches.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
f3cc9335e6 freedreno/a6xx: Set bin size per bin
It is not saved/restored by level 1 preemption with skipsaverestore=1,
so we need to set it for each bin.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
be6342633c freedreno/a6xx: Cleanup WFIs around RB_CCU_CNTL
This was only actually needed on the earliest a6xx (probably just
a630?).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
3aac51a6d5 freedreno/a6xx: De-open-code VFD_MODE_CNTL
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
2f82555efa freedreno/a6xx: Only emit VFD/PC_POWER_CNTL for a6xx
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Connor Abbott
c7a7f6dad8 tu: Add TU_DEBUG=hiprio
The same as FD_MESA_DEBUG=hiprio in freedreno.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Connor Abbott
1d2b479a3b tu: Allow being preempted on a7xx
This is only tested on a7xx so far, although it should work on a6xx too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Connor Abbott
3631f9ad62 tu/virtio: Make virtio_simple_ioctl take a vdrm_device
We need to do an ioctl in order to try to create a queue before the
tu_device is created.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Connor Abbott
700e26a448 tu: Emit CP_SET_AMBLE packets
Make sure skipsaverestore works.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Connor Abbott
db86c4c496 tu: Simplify device startup CS creation
We have a few different command streams we create at startup. Simplify
the initialization by creating a single sub_cs to allocate all of the
cs's out of and inlining structures where appropriate.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Connor Abbott
acdbfe9812 tu: Re-emit LRZ state before each bin
Similar to the bin size register, even though this is the same for each
bin it needs to be re-emitted to make skipsaverestore work.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:45 +00:00
Connor Abbott
b9d9fdb6d1 tu: Write bin size for each bin
While the register is constant for all bins in the render pass, it is
not saved and restored with level 1 preemption with skipsaverestore=1 so
it needs to be restored. Follow what the blob does and set it before
each bin.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:45 +00:00
Connor Abbott
4d75a4ac4b tu: Split out register setting from tu6_init_hw()
Split out the parts that will also have to be done in the bin restore
IB.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:45 +00:00
Connor Abbott
a9f88ff2af tu: Don't WFI after initializing RB_CCU_CNTL on a7xx
There's no reason to do this and the blob doesn't.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:45 +00:00