Commit graph

163306 commits

Author SHA1 Message Date
Samuel Pitoiset
ce0c70fb0c vulkan: ignore VkPipelineColorWriteCreateInfoEXT if the state is dynamic
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24601>
2023-08-11 23:38:55 +00:00
Erico Nunes
c43135d740 egl/drm: fix EGL_EXT_buffer_age with gbm contexts
Fix remaining dri2 check from 3d59f4cfcb, which caused gbm contexts to
not expose EGL_EXT_buffer_age anymore.

Fixes: 3d59f4cfcb ("egl/drm: Use IMAGE_DRIVER instead of DRI2_LOADER")

Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24630>
2023-08-11 21:50:21 +00:00
Alyssa Rosenzweig
ae81eb9d50 asahi: Legalize compression before blitting
Fixes invalid recursive blitting.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
7ac6176ea5 agx: Do not allow creating vec8
mem_access_bit_size needs to split up 64x4 into 2 loads. Fixes:

dEQP-VK.spirv_assembly.instruction.compute.64bit_compare.int64.comp_opiequal_vector

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
fd481d00d3 agx: Handle <32-bit local memory access
I don't know if this is possible to hit with GL, but it is with Vulkan. Fixes:

dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
aeffd22c30 agx: Handle f2f16_rtne like f2f16
TBD whether we can control round modes later on.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
4002ba95bb agx: Lower f2f16_rtz
Based on what VIR does.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
3634791baa agx: Fix 64-bit immediate moves
Don't truncate them in the builder. Fixes:

dEQP-VK.spirv_assembly.instruction.compute.convertutof.uint64_to_float32_4294967296

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
4d0233cb1d agx: Fix uadd_sat packing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
73657cd011 agx: Handle conversions to 8-bit
These can't be lowered by nir_lower_bit_sizes but it doesn't actually matter.
Fixes SPIR-V conversions tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
fa2a7cb2a8 agx: Lower f2u8/f2i8
The less 8-bit we need to emulate in the backend the better.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
b3ed5228b4 agx: Handle blocks with no predecessors
This can come up with loops with SPIR-V. Fixes:

dEQP-VK.spirv_assembly.instruction.compute.loop_control.none

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Asahi Lina
c247de37bb asahi: Fix incorrect BO bitmap reallocations
If the BO handle is greater than 2x what fits inside the current bitmap
size, then we end up overflowing. Make sure to always reallocate to a
large enough bitmap, not just 2x the previous size.

Found while replaying firefox apitraces with looping (which apparently
leaks a ton of objects, but that might just be apitrace).

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Asahi Lina
f1fedb72d3 asahi: Handle non-written RTs correctly
When a bound RT is not written to, we need to force the pass type to
translucent to ensure that this draw does not cull draws that do write
to that RT.

Fixes Inochi2D regression after c24b753378.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Mary
0f4e3a03fd agx: Move nir_lower_fragcolor out of agx_preprocess_nir
Do not apply "nir_lower_fragcolor" in the common code.

This fix a crash on agxv side when a frag shader have SSBO writes.

This is caused by "nir_lower_frag_color" assuming that every
"store_deref" will have a variable backing the
output.

Signed-off-by: Mary <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
3704caca0b agx: Stop setting forwarding bit
We need actual analysis to set it properly, and improperly setting it can cause
random data dependency hazards it turns out. Stop setting it. Fixes some flaky
tests with shuffle code inserted.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
09dfaf2c91 agx: Remove unused allocation
Relic from early RA attempts.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
ae440c9929 agx: Don't reuse ssa_to_reg across blocks
This avoids an entire class of bugs with live range splitting. Fixes with
AGX_MESA_DEBUG=demand:

   dEQP-GLES31.functional.separate_shader.random.8

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
d035908550 agx: Don't use ssa_to_reg across blocks
This is a footgun with live range spltiting.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
964a67fda4 agx: Assert invariant stated in the comment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
6909cb6379 agx: Use agx_replace_src
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
6447bf4cce agx: Stop setting registers after the shader
Leftover from before live range splitting. Should be a no-op.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
87121cf9a4 agx: Set phi sources in predecessors
This ensures correctness with live range splits. Now agx_set_sources is only for
non-phis where it makes sense.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
8cc96d64b0 agx: Fix accounting for phis
All affected shaders are in pubg. Presumably, with the new demand calculation,
RA is hitting a higher target thread count at the expense of a little more live
range splitting.

   total instructions in shared programs: 1773295 -> 1773310 (<.01%)
   instructions in affected programs: 6058 -> 6073 (0.25%)
   helped: 0
   HURT: 15
   Instructions are HURT.

   total bytes in shared programs: 11695360 -> 11695450 (<.01%)
   bytes in affected programs: 40496 -> 40586 (0.22%)
   helped: 0
   HURT: 15
   Bytes are HURT.

   total halfregs in shared programs: 530844 -> 530724 (-0.02%)
   halfregs in affected programs: 1785 -> 1665 (-6.72%)
   helped: 15
   HURT: 0
   Halfregs are helped.

   total threads in shared programs: 18909440 -> 18910400 (<.01%)
   threads in affected programs: 12480 -> 13440 (7.69%)
   helped: 15
   HURT: 0
   Threads are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig
d2224544d6 agx: Allow 64-bit memory regs
The mask is based on the format, which can be at most 32-bits per channel. So if
we have 64-bit loads/stores we're still using a 32-bit format with double the
bits set in the mask. This will fix validation fails with spilling.

No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
d0b966cb10 agx: Maintain ctx->max_reg while assigning regs
We can't calculate after since ssa_to_reg[] gets overwritten during live range
splits. Theoretical issue only, but let's fix it while squashing live range
splitting bugs.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
b973e38214 agx: Fix AGX_MESA_DEBUG=demand
No wonder it seemed like it wasn't doing anything!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
135f3c35c5 agx: Optimize logical_end removal
We know logical_end instructions are only at the end of the block (validated),
so by changing how we iterate the pass goes from O(instructions) to O(blocks)
which is strictly better.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
d459de85b7 agx: Optimize swaps of 2x16 channels
We can use extr to swap the low and high halves of a 32-bit register in one
instruction.

No shader-db changes, but it reduces xor's on a deqp I'm looking at. Yes, I'm
procrastinating on debugging deqps, how'd you guess?

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
efbdc31ce5 agx: Use compressed fadd/fmul encodings
See applegpu commit b9b3582 ("FBinaryInstructions have compressed encodings")

   total bytes in shared programs: 11717310 -> 11716524 (<.01%)
   bytes in affected programs: 317504 -> 316718 (-0.25%)
   helped: 196
   HURT: 0
   Bytes are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
a30c668e44 agx: Require an immediate for nest
There's no good reason to allow non-immediate nesting values, and this lets us
use the (smaller) mov_imm instruction without special casing. This matches what
Metal produces, so it seems like a good preference.

   total bytes in shared programs: 11720338 -> 11717310 (-0.03%)
   bytes in affected programs: 2341580 -> 2338552 (-0.13%)
   helped: 1385
   HURT: 0
   Bytes are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
85d6f162ad agx: Fix length bit confusion
Man, this expression was wrong. First of all, raw is 64-bit so our mask needs to
be too. Second, length is in bytes -- not bits -- so we need to multiply by 8 to
get something sensible. In effect, the old wrong expression would always use the
long encoding for ALU instructions... whoops. This particular bug probably goes
back to the very first version of agx_pack...

Massive improvement in code density. Noticed while comparing assembly with the
blob. It's my Saturday, I can pointless optimize if I want to.

   total bytes in shared programs: 12175112 -> 11720338 (-3.74%)
   bytes in affected programs: 11963800 -> 11509026 (-3.80%)
   helped: 16624
   HURT: 0
   Bytes are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
e83b708676 agx: Optimize out pointless else instructions
Now that they're in the right blocks, this is easy. Includes an informal proof
and the implementation itself is built around a finite state machine, which
together meant this code worked on its first try :~)

And hey, it's a pointless little instruction saving optimization I've wanted to
do for a while~

Major note is that this HAS to be done after register allocation, since it
doesn't update the control flow graph and would introduce critical edges
if it tried to actually deleted the else block. The intuitive reason for this is
simple: sometimes RA needs to insert instructions into the else block, even if
it was empty in the original NIR, so we always need an else block even if we can
delete it with this pass after RA.

   total instructions in shared programs: 1778390 -> 1776725 (-0.09%)
   instructions in affected programs: 268459 -> 266794 (-0.62%)
   helped: 1013
   HURT: 0
   Instructions are helped.

   total bytes in shared programs: 12185102 -> 12175112 (-0.08%)
   bytes in affected programs: 1927524 -> 1917534 (-0.52%)
   helped: 1013
   HURT: 0
   Bytes are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
782055106f agx: Use unconditional else instruction
Rather than duplicating the condition. This matches the blob, so is presumably
the most energy-efficient way of expressing the logic.

No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
41b7891673 agx: Put else instructions in the right block
According to Dougall's pseudocode, else_icmp operates as:

  if r0l == 0:
    r0l = n
  elif r0l == 1:
    if cc.compare(A[thread], B[thread]):
      r0l = 0
    else:
      r0l = 1

  exec_mask[thread] = (r0l == 0)

Notice that the comparison only happens when r0l == 1, that is, for threads that
are about to enter the else block. Threads that just executed the if body are
still active (r0l = 0) and skip the comparison. As such, the sources of
else_icmp are only read in the else block, and hence the whole instruction
should be placed in the else block for correctness with respect to live range
splitting.

shader-db is a wash, but shows some improvements due to correctly modelling the
liveness of the condition variable.

   total instructions in shared programs: 1778376 -> 1778390 (<.01%)
   instructions in affected programs: 14753 -> 14767 (0.09%)
   helped: 35
   HURT: 39
   Inconclusive result (value mean confidence interval includes 0).

   total bytes in shared programs: 12185018 -> 12185102 (<.01%)
   bytes in affected programs: 101522 -> 101606 (0.08%)
   helped: 35
   HURT: 39
   Inconclusive result (value mean confidence interval includes 0).

   total halfregs in shared programs: 531174 -> 531032 (-0.03%)
   halfregs in affected programs: 2320 -> 2178 (-6.12%)
   helped: 40
   HURT: 1
   Halfregs are helped.

   total threads in shared programs: 18909184 -> 18909440 (<.01%)
   threads in affected programs: 1792 -> 2048 (14.29%)
   helped: 2
   HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
5196558204 agx: Do not move bindless handles
NIR->AGX translation relies on bindless handles being vec2 instructions with a
constant first index. Moving the entire vec2 into the preamble would mess this
up, so tell nir_opt_preamble to never do this. It's still allowed to move the
offset calculation into the preamble, if it thinks that's beneficial.

Fixes dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
c252120239 agx: Fix shader info with sample mask writes
Otherwise the discard_agx isn't lowered.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Asahi Lina
c1e2200b70 asahi: Enable explicit coherency for G14D (multi-die)
It turns out we do need this explicit coherency dance for G14,
but only on G14D.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Janne Grunau
d6ee12a4d7 asahi,agx: Upload constant buffers immediately
The lifetime of the constant buffer's user_buffer is not guaranteed
to last until agx_upload_uniforms.
Fixes the same ASAN issue mesa/mesa!21685 is trying to address.

Fixes: 080b05e29e ("asahi: Add Gallium driver")
Signed-off-by: Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
f4fd4d4d50 agx: Fix atomics with no destination
We need to:

* properly null out the dest in DCE.
* not assert out when packing with null dest

Fixes potential reg pressure blow up with atomics that don't use their
destinations, though I don't see shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
9da8dc47f9 agx/dce: Use the helper
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
0d7b8bfce5 agx: Don't lower load_local_invocation_index
We have an SR for it, which can save a bit of math. This came up while working
on the spiller.

   total instructions in shared programs: 1778396 -> 1778376 (<.01%)
   instructions in affected programs: 3036 -> 3016 (-0.66%)
   helped: 10
   HURT: 3
   Instructions are helped.

   total bytes in shared programs: 12185182 -> 12185018 (<.01%)
   bytes in affected programs: 38640 -> 38476 (-0.42%)
   helped: 18
   HURT: 2
   Bytes are helped.

   total halfregs in shared programs: 531218 -> 531174 (<.01%)
   halfregs in affected programs: 471 -> 427 (-9.34%)
   helped: 6
   HURT: 0
   Halfregs are helped.

   total threads in shared programs: 18909056 -> 18909184 (<.01%)
   threads in affected programs: 1280 -> 1408 (10.00%)
   helped: 2
   HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Janne Grunau
3f8894b0f7 asahi,agx: Fix stack buffer overflow in agx_link_varyings_vs_fs
Discovered while running dEQP-EGL under address sanitizer.

Fixes: f3877f56ba ("asahi,agx: Rewrite varying linking")
Signed-off-by: Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Asahi Lina
eafd35e458 asahi: Force linear for SHARED buffers with no/implicit modifier
Consumers might not pass through the modifier information in this case.

Fixes XWayland/mutter using dma-buf v4 feedback (though the fact they
try to use implicit modifiers is likely a bug on their end, and will
decrease performance).

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig
3e5d2f0c1b asahi,agx: Respect no16 even for I/O
Don't call lower_mediump_io for no16. This is helpful for debugging and soon
driconf-shaming apps with broken precision qualifiers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Asahi Lina
721aa39ad9 asahi: Impose limits on resource shadowing
Apps can have pathological use cases where huge resources are shadowed
repeatedly. An app that alternately writes to a resource and then uses
it to draw can create an unbounded amount of shadow BOs.

To fix this, introduce both a maximum resource size for shadowing, and a
maximum cumulative size that resource may be shadowed before we start
flushing readers. The flush path then clears the counter, as does the
happy path where there are no readers left after flushing writers.

Fixes massive memory bloating in Firefox and probably others.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Asahi Lina
9d668f87d3 asahi: Print info about shadowed resources
If resource and perf debugging are both enabled, this prints resource
info for shadowed resources.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Asahi Lina
ccbd125468 asahi: Always use resource size, not BO size
BOs can be oversized, as they can come from the BO cache. Make sure to
always use the resource layout size, not the BO size, when we need this
for some reason.

This fixes BO shadowing creating overlarge BOs, and also the attachment
size for submissions (probably doesn't matter, but it's more correct now).

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Asahi Lina
f8f4f466f7 asahi: Fix race in BO stats accounting
These counters are accessed without locking, so they need to be atomic.
Should be cosmetic only.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00
Asahi Lina
9762c55589 asahi: Do not overallocate BOs by more than 2x
This is not likely to be useful, and might take over a correctly-sized
BO that is going to be reused later.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
2023-08-11 20:31:27 +00:00