Commit graph

24723 commits

Author SHA1 Message Date
Brian Paul
0ddc4dbe43 draw: use flatfirst variable 2009-06-18 23:00:37 -06:00
Brian Paul
9205a871e7 draw: remove debug code 2009-06-18 22:51:41 -06:00
Brian Paul
af5fff9c23 draw: fix first provoking vertex mode for quads, quad strips and polygons 2009-06-18 22:48:51 -06:00
Brian Paul
950171be3c draw: fix first provoking vertex mode for unfilled quads 2009-06-18 22:47:46 -06:00
Brian Paul
601065f153 mesa: fix first provoking vertex mode for unfilled tri strips 2009-06-18 22:45:57 -06:00
Brian Paul
c70a529d7c draw: clean up indentation 2009-06-18 18:33:29 -06:00
Thomas Hellstrom
0342229289 gallium dri st: Probe the driver for supported surface formats.
This is done when constructing the fbconfigs, and the result is saved
for window system framebuffer creation.

Note: For dri2 the server needs to have an identical format selection
logic. Otherwise the dri state-tracker and the xorg driver (state-tracker)
will disagree on which format to use for the attachments. Some more work
is needed in this area.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2009-06-17 03:07:01 +02:00
Thomas Hellstrom
c9f19571da mesa driconf: Add macro to specify an option with a quoted default value.
The default values true and false will expand to "1" and "0" when
gcc -std=c99, causing bool option defaults to generate runtime failures.

One solution is to specify bool option defaults quoted as "true" and "false".
Add a macro to assist this.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2009-06-17 03:07:00 +02:00
Jakob Bornecrantz
edbec6b112 progs/rbug: Add small program to add block rules 2009-06-18 14:36:19 +02:00
Eric Anholt
3addc4e307 i965: Add decode for the G4X x,y offset in surface state. 2009-06-17 21:01:48 -07:00
Eric Anholt
6c3f696891 i965: Fix up texture layout for small things with wide pitches (tiled)
We were packing according to the pitch, while the hardware appears to base
it on the base level width.

With this and the previous commit, fbo-cubemap now matches untiled behavior.
2009-06-17 21:01:48 -07:00
Eric Anholt
0f328c90db i965: Fall back or appropriately adjust offsets of drawing to tiled regions.
3D rendering to tiled textures was being done with non-tile-aligned offsets.
The G4X hardware has fields to let us support it easily and correctly, while
the pre-G4X hardware requires a path full of suffering, so we just fall back.
2009-06-17 21:01:48 -07:00
Dave Airlie
46000cecc3 r300: use vbo_split_prims to split up large vertex buffers.
This lets ut2004 avoid hitting the elt warning.
2009-06-18 13:25:38 +10:00
Eric Anholt
bd10f0e84f i965: Fix tiling for FBO depth attachments by making DEPTH_COMPONENT Y tiled.
This may hurt if miptree relayout occurs, since we can't blit Y tiled
objects.  But it corrects depth tests on FBOs using textures.
2009-06-17 20:19:19 -07:00
Dave Airlie
b165fa7d45 radeon: don't re-add BOs to validate list
if its on the list its on the list don't go readding it.

multitexturing from the same texture could cause this.
2009-06-18 13:16:06 +10:00
Brian Paul
3817a54912 glsl: call _mesa_postprocess_program(), disabled 2009-06-17 09:58:29 -06:00
Brian Paul
516d20fd26 mesa: silence warning 2009-06-17 09:58:29 -06:00
Brian Paul
ec6ad7ba3c mesa: added _mesa_postprocess_program() to aid shader debugging 2009-06-17 09:58:29 -06:00
Jerome Glisse
f806a03361 radeon: Flush command buffer on viewport change
We flush the command buffer so we don't emit mixed
state (with new and previous buffer size) command
buffer, this is especialy affecting zbuffer states.
2009-06-17 16:33:14 +02:00
Jerome Glisse
2506c4e8b1 r300: don't emit vap index offset on r5xx hw when using cs
vap index offset is programmed to 0 by the kernel, it
would add work to kernel checker to allow userspace
programming of this so it's now disallowed with CS
on KMS.
2009-06-17 13:54:09 +02:00
Dave Airlie
77506dac8e GLX: attempt to fix glean makeCurrent test cases.
Two parts to this:

One we don't keep pointers to possibly freed memory anymore once we unbind the
drawables from the context. Brian I need to figure out what the comment
you made there, can we get a glean/piglit test so we can fix it properly?

If the new gc is the same as the oldGC, we call the unbind even though
we just bound it in that function. doh.
2009-06-17 13:59:28 +10:00
Dave Airlie
856221d699 radeon: fix warnings in wrapper with libdrm 2009-06-17 11:12:57 +10:00
Brian Paul
8d48222791 Merge branch 'mesa_7_5_branch'
Conflicts:

	src/mesa/main/api_validate.c
2009-06-16 18:25:52 -06:00
Roland Scheidegger
4ef1f8e3b5 i965: handle OPCODE_SWZ in the glsl path
glsl compiler will not generate OPCODE_SWZ, and as a first step it would
be translated away to a MOV anyway (why?), but later internally this opcode is
generated (for EXT_texture_swizzling).
2009-06-16 21:40:41 +02:00
Brian Paul
1510c3cae1 docs: minor relnotes clean-up 2009-06-15 16:44:26 -06:00
Brian Paul
70d247c69b Merge branch 'arb_map_buffer_range'
Conflicts:

	docs/relnotes-7.6.html
	src/mesa/main/mtypes.h
2009-06-15 16:42:42 -06:00
Brian Paul
01f7bda44c mesa: revert some recent VBO buffer object refcounting changes
Reverts part of commit d7ea9ddf58.
We were calling _mesa_reference_buffer_object() on some heap-allocated
memory that was uninitialized and could trigger an assertion.
We can actually go back to "looser" ref counting of the Null/default
buffer object in these cases.
2009-06-15 10:58:04 -06:00
Brian Paul
b0d874bfbe mesa: regenerated gl_mange.h file 2009-06-15 10:47:07 -06:00
Roland Scheidegger
63c407db3e enable ARB_half_float_pixel for intel drivers 2009-06-15 18:31:03 +02:00
Roland Scheidegger
4ed2c0dddc intel: fix (cosmetic) typo flag used twice 2009-06-15 18:30:51 +02:00
Thomas Hellstrom
f5888d9ca5 Merge branch 'mesa_7_5_branch'
Conflicts:

	progs/util/extfuncs.h
2009-06-15 11:43:48 +02:00
Maciej Cencora
e0eafde746 r300: fix 3D textures 2009-06-15 01:07:19 +02:00
Jakob Bornecrantz
6530fabb93 Merge branch 'mesa_7_5_branch' 2009-06-14 06:32:47 +02:00
Jakob Bornecrantz
210ad58ee3 trace: Don't write state objects to file if dumping is not set 2009-06-14 06:07:50 +02:00
Keith Whitwell
0cce6d7e33 tgsi: correct handling of return value from util_vsnprintf
We were failing to deal with:
  - vsnprintf returns negative value on error.
  - vsnprintf returns the number of chars that *would* have been
    written on truncation.
2009-06-26 13:43:10 +01:00
Dave Airlie
0952645fe0 r200: make use of DMA buffers for Elts a lot better.
This allows us to return the unused portion of the dma buffer
to the allocator instead of wasting nearly 16k a pop.
2009-06-26 15:09:12 +10:00
Dave Airlie
db54579628 r200: only emit unitneeded textures 2009-06-26 15:09:11 +10:00
Joakim Sindholt
622858884f r300-gallium: organize fragment/vertex shaders
Appart from separating r3xx/r5xx fragment shaders, a more consistent
naming scheme has been applied. From now on:
r300 = all chips
r3xx = R300/R400 only
r5xx = R500 only
This way r300_fragment_shader is the master struct, and the structs
r3xx_fragment_shader and r5xx_fragment_shader inherits it.
2009-06-26 01:13:06 +02:00
Vinson Lee
450b20d1ef gallium: Add PIPE_OS_APPLE token. 2009-06-25 09:52:50 -06:00
Jakob Bornecrantz
e99d13bbc6 progs/tests: Add yet another mipmap test 2009-06-14 01:44:34 +02:00
Roland Scheidegger
43b3b745e4 radeon: fix hw texture limits
still always enable max, but the right values this time.
More work should probably be done for saner limits without mm, and/or
dri conf option allow_large_textures (which is ignored) removed.
3D limit on r100 is pretty arbitrary as still handled by swrast anyway.
Also fix r300 limits (except 3d I've no idea what the max is anyway so
keep using mesa default).
2009-06-25 15:57:33 +02:00
Dave Airlie
cdbcb051d9 radeon/r200: add some hw texture limits 2009-06-25 13:26:52 +10:00
Dave Airlie
69fd0cbaa2 radeon: fix stupidity in cs space check code.
This was already correct in the GEM code
2009-06-25 12:13:17 +10:00
Brian Paul
bc5c40d7d9 intel: fix additional merge conflicts missed in previous commit 2009-06-24 08:57:48 -06:00
Brian Paul
a04af335a4 Merge branch 'mesa_7_5_branch'
Conflicts:

	src/mesa/drivers/dri/i915/i915_tex_layout.c
	src/mesa/drivers/dri/i965/brw_wm_glsl.c
	src/mesa/drivers/dri/intel/intel_buffer_objects.c
	src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
	src/mesa/drivers/dri/intel/intel_pixel_draw.c
	src/mesa/main/enums.c
	src/mesa/main/texstate.c
	src/mesa/vbo/vbo_exec_array.c
2009-06-24 08:54:37 -06:00
Jakob Bornecrantz
d60b2c6855 identity: Add new identity driver
This driver does no transformation of the gallium calls
	going to the real driver, like the identity matrix. It is
	intended to be the basis for transforming and/or debug
	drivers like trace and rbug.

	Authors of this patch are:
		Michal Krol, orignal heavy lifting.
		José Fonesca, object wrapping code stolen from trace.
		Jakob Bornecrantz, put it all toghether and renamed a stuff.
2009-06-24 13:04:56 +02:00
Eric Anholt
b8e638d489 i965: Disable texture tiling by default.
I haven't fixed all the regressions yet, and it'll be easy to re-enable when
the known problems are fixed.
2009-06-23 19:31:43 -07:00
Eric Anholt
b72dea5441 i965: Set the max index buffer address correctly according to the docs.
It's the last addressable byte, not the byte after the end of the buffer.
2009-06-23 19:31:13 -07:00
Eric Anholt
d43599afef i965: Don't set a reserved bit in MI_FLUSH.
I noticed this when this MI_FLUSH showed up in IPEHR for the ut2004 hang.
Not setting the reserved bit didn't help, though.
2009-06-23 19:31:13 -07:00
Eric Anholt
5ca800e100 dri2: Refresh the fake front contents after glXSwapBuffers().
Bug #19177.

Reviewed by: Ian Romanick <ian.d.romanick@intel.com>
2009-06-23 19:31:12 -07:00