Commit graph

42659 commits

Author SHA1 Message Date
Jakob Bornecrantz
ca8a91ff7e util: Don't destroy shaders null shaders
Fixes regression from a08e612fd8
2011-02-26 02:32:22 +01:00
Jakob Bornecrantz
a08e612fd8 util: Don't create array texture shaders if the driver doesn't support it 2011-02-26 00:50:52 +01:00
Kenneth Graunke
58f7c9c72e i965/fs: Initial plumbing to support TXD.
This adds the opcode and the code to convert ir_txd to OPCODE_TXD;
it doesn't actually add support yet.
2011-02-25 15:30:45 -08:00
Kenneth Graunke
2830b1ae90 i965/fs: Complete TXL support on gen5+.
Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was
never handled.
2011-02-25 15:30:45 -08:00
Kenneth Graunke
4ddd11aad6 i965/fs: Complete TXL support on gen4.
Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was
never handled.
2011-02-25 15:30:45 -08:00
Kenneth Graunke
e54d62b896 i965/fs: Use a properly named constant in TXB handling.
The old value, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE makes it sound like we're
doing a non-bias texture lookup.  It has the same value as the new constant
BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE, so there should be no
functional changes.
2011-02-25 15:30:45 -08:00
Kenneth Graunke
a3cd542894 i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.
From volume 4, page 161 of the public i965 documentation.
2011-02-25 15:30:45 -08:00
Jerome Glisse
b0e8aec5ab gallium/tgsi: shuffle ureg_src structure to work around gcc4.6.0 issue
There is an issue with gcc 4.6.0 that leads to segfault/assert with mesa
due to ureg_src size, reshuffling the structure member to better better
alignment work around the issue.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47893

7.9 + 7.10 candidate

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2011-02-25 12:44:07 -05:00
Jerome Glisse
8e17adfdbd gallium/st: place value check before value is use
7.9 & 7.10 candidate

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2011-02-25 11:49:23 -05:00
Dave Airlie
179ff0551c gallium/util: add 1d/2d mipmap generation support
so far only hw mipmap generation is testing on softpipe,
passes test added to piglit.

this requires another patch to mesa to let array textures mipmaps
even start to happen.
2011-02-25 16:06:15 +10:00
Vinson Lee
eb17802386 scons: Reduce all Cygwin platform names to 'cygwin'.
platform.system in SCons on Cygwin includes the OS version number.
Windows XP - CYGWIN_NT-5.1
Windows Vista - CYGWIN_NT-6.0
Windows 7 - CYGWIN_NT-6.1

Reduce all Cygwin platform variants to just 'cygwin' so anything
downstream can simply use 'cygwin' instead of the different full
platform names.
2011-02-24 19:49:37 -08:00
Dave Airlie
b2413de916 r600g: explicity set sign bits for RGTC 2011-02-25 09:18:42 +10:00
Dave Airlie
c9bca01819 r600g: bc 4/5 or rgtc textures need to be tiled as well.
Make the s3tc upload code more generic.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-25 09:18:42 +10:00
Dave Airlie
79ad6f5375 r300g: explicit sign bits on RGTC textures 2011-02-25 09:18:41 +10:00
Kenneth Graunke
e6e5c1f46d i965: Increase Sandybridge point size clamp in the clip state.
255.875 matches the hardware documentation.  Presumably this was a typo.

NOTE: This is a candidate for the 7.10 branch, along with
      commit 2bfc23fb86.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-24 11:23:08 -08:00
Neil Roberts
c0ad70ae31 intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebuffer
In the case where glBlitFramebuffer is being used to copy to a texture
without scaling it is faster if we can use the hardware to do a blit
rather than having to do a texture render. In most of the drivers
glCopyTexSubImage2D will use a blit so this patch makes it check for
when glBlitFramebuffer is doing a simple copy and then divert to
glCopyTexSubImage2D.

This was originally proposed as an extension to the common meta-ops.
However, it was rejected as using the BLT is only advantageous for Intel
hardware.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33934
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24 16:43:39 +00:00
Christoph Bumiller
11b9f4439c nvc0: fix PointCoord enable in FP header 2011-02-24 17:35:36 +01:00
Christoph Bumiller
d0caaba370 nvc0: change TGSI CMP translation to use slct
Saves us the explicit compare instruction needed with selp.
2011-02-24 17:35:36 +01:00
Christoph Bumiller
b0bf4ee85f nvc0: sprite coord enable is per GENERIC, not overall index 2011-02-24 17:35:36 +01:00
Christoph Bumiller
9dd7d0803e nvc0: fix new_value calls using type instead of size 2011-02-24 17:35:36 +01:00
Christoph Bumiller
1a82971393 nvc0: set local memory usage info in shader header
Before this, l[] access was a no-op.
2011-02-24 17:35:36 +01:00
Christoph Bumiller
b5f04b2008 nvc0: don't fold loads from local memory 2011-02-24 17:35:36 +01:00
Christoph Bumiller
9612139907 nvc0: presin and preex2 can load from const space 2011-02-24 17:35:36 +01:00
Christoph Bumiller
f017483553 nvc0: kick out empty live ranges
They affect overlap tests even though they're actually empty.
2011-02-24 17:35:35 +01:00
Christoph Bumiller
cd47f10c90 nvc0: preemptively insert branch at ENDIF
Might be necessary if a block sneaks in somewhere, like a common
block for moves of phi sources after a loop break.

This is harmless and normally will be removed before emission.
2011-02-24 17:35:35 +01:00
Christoph Bumiller
4377657f8e nvc0: correct allocation of constrained registers
In linear scan we can't allocate multiple values with different
live ranges at the same time to assign them consecutive regs.

Maybe we should just switch to graph coloring for all values ...
2011-02-24 17:35:35 +01:00
Christoph Bumiller
67c7aefea3 nvc0: sync textures with render targets ourselves
Fixes for example piglit/fbo-flushing and nexuiz' bloom effect.
2011-02-24 17:35:35 +01:00
Christoph Bumiller
a6ea37da4b nvc0: improve userspace fencing
Before, there were situations in which we never checked the fences
for completion (some loading screens for example) and thus never
released memory.
2011-02-24 17:35:35 +01:00
Christoph Bumiller
410a13c5ce nvc0: values for undefined outputs must have file GPR 2011-02-24 17:35:35 +01:00
Christoph Bumiller
1579017b08 nvc0: multiply polygon offset units by 2
Wasn't sure if this still was necessary because the piglit test
started to fail at some point on nv50 where we already do this.
2011-02-24 17:35:35 +01:00
Christoph Bumiller
7d8ff54feb nvc0: fix SSG 2011-02-24 17:35:35 +01:00
Christoph Bumiller
88066d62ae nvc0: don't visit target blocks of a loop break multiple times 2011-02-24 17:35:35 +01:00
Christoph Bumiller
3d190e44de nvc0: don't overwrite phi sources at the end of a loop
Except the reference to its own result.
2011-02-24 17:35:35 +01:00
Fabian Bieler
728695b435 gallium/utils: Fix vertex element setup
Check if element was translated per element instead of per buffer.
2011-02-24 15:05:10 +01:00
José Fonseca
369ece1702 svga: Ensure rendertargets and textures are always rebound at every command buffer start.
The svga_update_state() mechanism is inadequate as it will always end up
flushing the primitives before processing the SVGA_NEW_COMMAND_BUFFER
dirty state flag.
2011-02-24 14:00:13 +00:00
Chris Wilson
f19439940c i965: Remember to pack the constant blend color as floats into the batch
Fixes regression from aac120977d.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24 12:59:52 +00:00
Chris Wilson
5ce0f7f109 intel: Reset the buffer offset after releasing reference to packed upload
Fixes oglc/vbo(basic.bufferdata)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24 12:29:51 +00:00
Chris Wilson
135ccb2dae i965: Unmap the correct pointer after discontiguous upload
Fixes piglit/fbo-depth-sample-compare:

==14722== Invalid free() / delete / delete[]
==14722==    at 0x4C240FD: free (vg_replace_malloc.c:366)
==14722==    by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695)
==14722==    by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722==    by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722==    by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722==    by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722==    by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722==    by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722==    by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722==    by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==    by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==    by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==  Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd
==14722==    at 0x4C244E8: malloc (vg_replace_malloc.c:236)
==14722==    by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256)
==14722==    by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722==    by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722==    by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722==    by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722==    by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722==    by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722==    by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722==    by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==    by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==    by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24 10:58:22 +00:00
Chris Wilson
a2029a78c3 intel: Protect against waiting on a NULL render target bo
If we fall back to software rendering due to the render target being
absent (GPU hang or other error in creating the named target), then we
do not need to nor should we wait upon the results.

Reported-by: Magnus Kessler <Magnus.Kessler@gmx.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34656
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24 10:12:37 +00:00
Dave Airlie
69d969e8fa r600g: EXT_texture_array support.
This adds EXT_texture_array support to r600g, it passes the piglit
array-texture test but I suspect may not be complete.

It currently requires a kernel patch to fix the CS checker to allow
these, so you need to use R600_ARRAY_TEXTURE=true for now
to enable them.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-24 13:26:28 +10:00
Dave Airlie
13f5a4d316 st/mesa: treat 1D ARRAY upload like a depth or 2D array upload.
This is because the HW doesn't always store a 1D array like a
2D texture, it more likely stores it like 2D texture (i.e.
alignments etc).

This means we upload each slice separately and let the driver
work out where to put it.

this might break nvc0 as I can't test it, I have only nv50 here.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-24 13:26:16 +10:00
Vinson Lee
100cd214e3 scons: Fix Cygwin platform names.
Fixes immediate Python exceptions with SCons on Cygwin.
2011-02-23 18:21:14 -08:00
Jakob Bornecrantz
8fb0ecd0cf i915g: Lazy emit dynamic state 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz
b9baad2aff i915g: Lazy emit immediate state 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz
69cfc16cb6 i915g: Disable LIS7 state updates for now 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz
42b8b2be85 i915g: Clean up in i915_state_immediate 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz
481fad1552 i915g: Remove outdated comment 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz
fbd681f1a0 i915g: Use dump function in sw winsys 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz
fc77dee0bd i915g: Enable mirror repeat wrap mode 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz
4407e5078f i915g: Always set vbo to flush on flushes
Reported-by Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24 00:26:02 +00:00