Commit graph

57299 commits

Author SHA1 Message Date
Ian Romanick
c9edd661c4 wmesa: Don't call _mesa_enable_._._extensions and _mesa_enable_sw_extensions
_mesa_enable_sw_extensions enables all the extensions (and more) that
the others enable.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-06-28 13:35:21 -07:00
Ian Romanick
89cf6e6273 x11: Don't call _mesa_enable_._._extensions and _mesa_enable_sw_extensions
_mesa_enable_sw_extensions enables all the extensions (and more) that
the others enable.  Also, don't duplicate the DXTn checks.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-06-28 13:35:21 -07:00
Ian Romanick
0b9398c74f i965: Merge the two GEN >= 6 extension enable blocks
There's no reason for these blocks to be separate.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-28 13:35:21 -07:00
Ian Romanick
ae66a656fd i965: Move GEN >= 4 extensions into the "always on" list
This copy of the source file is only used for GEN >= 4, so extensions
that are enabled for GEN >= 4 are always enabled.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-28 13:35:21 -07:00
Ian Romanick
4ed976f6b5 i965: Move GEN >= 3 extensions into the "always on" list
This copy of the source file is only used for GEN >= 4, so extensions
that are enabled for GEN >= 3 are always enabled.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-28 13:35:20 -07:00
Ian Romanick
e621208e29 i915: Remove GEN >= 4 extension support
This copy of the source file is only used for GEN <= 3, so remove the
dead code.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-28 13:35:20 -07:00
Kenneth Graunke
745f6c692c i965: Split surface format code into a new file (brw_surface_formats.c).
brw_wm_surface_state.c has gotten rather large and unwieldy.  At this
point, it consists of two separate portions:

1. Surface format code

   This includes the giant table of surface formats and what features
   they support on each generation, as well as the code to translate
   between Mesa formats and hardware formats.

   This is used across all generations.

2. Binding table (SURFACE_STATE) related code.

   This is the code to generate SURFACE_STATE entries for renderbuffers,
   textures, transform feedback buffers, constant buffers, and so on, as
   well as the code to assemble them into binding tables.

   This is only used on Gen4-6; gen7_surface_state.c has Gen7+ code.

Since the two are logically separate, and one is reused on every
generation while the other is not, it makes a lot of sense to split
them out.  It should also make finding code easier.

No code is changed by this patch.  I simply copied the file then deleted
portions of both.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-06-28 13:35:11 -07:00
Alex Deucher
c309e64db8 radeonsi: add kabini pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:17:27 -04:00
Alex Deucher
b6b1346691 radeonsi: add bonaire pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:17:18 -04:00
Alex Deucher
d669992e35 radeonsi: disable 2D tiling on CIK for now
Causes GPU hangs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:17:10 -04:00
Alex Deucher
1357624abc radeonsi: add llvm processor names for CIK
Requires updated llvm.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:17:00 -04:00
Alex Deucher
234d81e6b2 radeonsi: emit PA_SC_RASTER_CONFIG[_1] on cik
Use the golden values for each asic.

Todo: update Kabini and Kaveri.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:16:53 -04:00
Alex Deucher
9d8ad222c6 radeonsi: PA_CL_ENHANCE is privileged on CIK
Needs to be and is set by the kernel.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:16:46 -04:00
Alex Deucher
72c10be3a7 radeonsi: update surface sync packet emit for CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:16:35 -04:00
Alex Deucher
f2a9bd8084 radeonsi: store chip class in the pm4 struct
Will be used for asic specific pm4 behavior.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:16:27 -04:00
Alex Deucher
3a47f1945f radeonsi: properly handle DB tiling setup on CIK
On CIK, DB switches back to using per-surface tiling
parameters rather than the tile index used on SI.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:16:17 -04:00
Alex Deucher
8c903f5df9 radeonsi: emit additional shader pgm rsrc registers for CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:16:10 -04:00
Alex Deucher
59e4fe0b75 radeonsi: emit TA_BC_BASE_ADDR_HI for border color on CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:16:03 -04:00
Alex Deucher
b363a45c54 radeonsi: fix VGT_PRIMITIVE_TYPE emit for CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:15:54 -04:00
Alex Deucher
ecb679a8d3 radeonsi: register updates for CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:15:46 -04:00
Alex Deucher
deb2358243 radeonsi: initial PM4 changes for CIK
note which packets are removed and add new ones.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:15:36 -04:00
Alex Deucher
f29f206c93 radeonsi: initial support for CIK chips
Add the infrastructure to differentiate them.
Just treat them like SI for now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:15:28 -04:00
Alex Deucher
5b3f1ea933 radeonsi: rename SI chip class from TAHITI to SI
Covers the entire family.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 15:15:20 -04:00
Tom Stellard
47e35eff9d r600g: Fix build
Broken since 2840bec56f when opencl is
disabled.
2013-06-28 11:11:43 -07:00
Anuj Phogat
ee723ffabb mesa: Return ZeroVec/dummyReg instead of NULL pointer
Assertions are not sufficient to check for null pointers as they don't
show up in release builds. So, return ZeroVec/dummyReg instead of NULL
pointer in get_{src,dst}_register_pointer(). This should calm down the
warnings from static analysis tool.

Note: This is a candidate for the 9.1 branch.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-06-28 10:53:43 -07:00
Tom Stellard
bee49cb0ec mesa: Fix build with older gcc since update of glext.h
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-06-28 08:49:06 -07:00
Tom Stellard
2840bec56f r600g/compute: Accept LDS size from the LLVM backend
And allocate the correct amount before dispatching the kernel.

Tested-by: Aaron Watry <awatry@gmail.com>
2013-06-28 08:33:11 -07:00
Tom Stellard
2639fca1f0 r600g/compute: Move compute_shader_create() function into evergreen_compute.c
Tested-by: Aaron Watry <awatry@gmail.com>
2013-06-28 08:33:11 -07:00
Brian Paul
ba4979810f svga: pass svga_compile_key by reference instead of value
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-28 08:38:00 -06:00
Brian Paul
74e8a7d1dd svga: use switch statement in svga_shader_type()
Safer in case the PIPE_SHADER_x tokens get renumbered (as Marek
wanted to do).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-28 08:37:59 -06:00
Chia-I Wu
24b05ff158 ilo: clean up states that use ilo_view_surface
Use variables that are easier to remember what they are.
2013-06-28 15:01:00 +08:00
Chia-I Wu
2c9b6a2164 ilo: remove ilo_cbuf_state::count
We can derive it from enabled_mask.
2013-06-28 15:01:00 +08:00
Chia-I Wu
7ea3ed81c8 ilo: clean up ilo_set_constant_buffer()
Add loops that will be optimized away.
2013-06-28 15:01:00 +08:00
Chia-I Wu
11d283cde9 ilo: clean up states that take a start_slot
They are similar, so clean them up to make them look similar.
2013-06-28 15:00:42 +08:00
Vinson Lee
def634979d glsl: Initialize member variable is_ubo_var in constructor.
Fixes "Uninitialized scalar field" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-06-27 21:51:32 -07:00
Chia-I Wu
20c691b936 ilo: use shorter names for dirty flags
The new names match those of ilo_context's members respectively, and are
shorter.
2013-06-28 10:44:51 +08:00
Chia-I Wu
cabc7b44c0 ilo: track if primitive restart has changed
Re-emit 3DSTATE_INDEX_BUFFER to enable/disable primitive restart.
2013-06-28 10:44:38 +08:00
Chia-I Wu
e071812e46 ilo: avoid potential dangling pointer dereference
Set pipe_draw_info to NULL after draw_vbo().
2013-06-28 10:11:49 +08:00
Ian Romanick
c74a7eb9c5 mesa: Remove GL_EXT_clip_volume_hint
As far as I can tell, no driver has enabled this extension since c6499a7
back in 2007.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-27 18:14:33 -07:00
Chad Versace
6b676e6634 i965,i915: Return early if miptree allocation fails
If allocation fails in intel_miptree_create_layout(), don't proceed to
dereference the miptree. Return an early NULL.

Fixes static analysis error reported by Klocwork.

Note: This is a candidate for the 9.1 branch.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-06-27 13:16:47 -07:00
Roland Scheidegger
670f829102 llvmpipe: handle offset_clamp
This was just ignored (unless for some reason like unfilled polys draw was
handling this).
I'm not convinced of that code, putting the float for the clamp in the key
isn't really a good idea. Then again the other floats for depth bias are
already in there too anyway (should probably have a jit_context for the
setup function), so this is just a quick fix.
Also, the "minimum resolvable depth difference" used isn't really right as it
should be calculated according to the z values of the current primitive
and not be a constant (of course, this only makes a difference for float
depth buffers), at least for d3d10, so depth biasing is still not quite right.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-27 19:06:40 +02:00
Roland Scheidegger
b04a295a4a llvmpipe: remove never reached code for timestamp queries.
timestamp queries are always binned in an active scene, therefore
always have a result.
2013-06-27 19:06:40 +02:00
Roland Scheidegger
59b8689d37 llvmpipe: fix a bug in opaque optimization
If there are queries active the opaque optimization reseting the bin needs to
be disabled.
(Not really tested since the bug was discovered by code inspection not
an actual test failure.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-27 19:06:40 +02:00
Vinson Lee
f12e551810 radeonsi/compute: Fix memory leak in radeonsi_launch_grid.
Fixes "Resource leak" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
2013-06-27 10:03:33 -07:00
Tom Stellard
0e990736f3 clover: Fix build with LLVM 3.4
Reported on IRC by lordheavy
2013-06-27 10:03:33 -07:00
Bill York
191795eaf1 docs: updated instructions for Mesa on Windows
Signed-off-by: Brian Paul <brianp@vmware.com>
2013-06-27 09:49:41 -06:00
Matthew McClure
e87fc11cac postprocess: handle partial intialization failures.
This patch fixes segfaults observed when enabling the post processing
features. When the format is not supported, or a texture cannot be
created, the code must gracefully handle failure and report the error to
the calling code for proper failure handling.

To accomplish this the following changes were made to the filters.h
prototypes:

- bool return for pp_init_func
- Added pp_free_func for filter specific resource destruction

Fixes segfaults from backtraces:

* util_destroy_blit
  pp_free

* u_transfer_inline_write_vtbl
  pp_jimenezmlaa_init_run
  pp_init

This patch also uses tgsi_alloc_tokens to allocate temporary tokens in
pp_tgsi_to_state, instead of allocating the array on the stack. This
fixes the following stack corruption segfault in pp_run.c:

* _int_free
  aaline_delete_fs_state
  pp_free

Bug Number: 1021843
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-06-27 09:44:29 -06:00
Brian Paul
482c43a946 glx: return True/False instead of GL_TRUE/GL_FALSE
Just to be consistent with the functions' Bool return type.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-27 07:48:19 -06:00
Brian Paul
d171bc9d19 glx: move declarations before code
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-27 07:48:18 -06:00
Brian Paul
d43548ca37 mesa: move declarations before code
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-27 07:48:18 -06:00