Commit graph

187810 commits

Author SHA1 Message Date
Samuel Pitoiset
c82b8a8153 radv: stop ignoring shader stages that don't need to be imported with GPL
The Vulkan specification has been updated since I wrote this and it's
invalid now.

This marks some tests as expected failures because they are invalid
now and they will be removed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28692>
2024-04-12 06:24:43 +00:00
Patrick Lerda
2b6993cb71 r300: fix r300_draw_elements() behavior
Indeed, the pointer processed by r300_upload_index_buffer() was not the right one.
This is the reason why "deqp-gles2 --deqp-case=dEQP-GLES2.functional.draw.draw_elements.indices.user_ptr.index_byte"
was failing (the logs are below). This change corrects this issue and makes the related deqp tests work properly.

This change considers that r300_upload_index_buffer() sets indexBuffer to NULL. The indexBuffer resource
should be properly freed once the buffer is processed. This is required to avoid another refcnt imbalance
(another kind of memory leak).

==9962==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x60200000721f at pc 0x7fd57b54a9a0 bp 0x7fffd2c39290 sp 0x7fffd2c38a40
READ of size 30 at 0x60200000721f thread T0
    #0 0x7fd57b54a99f in __interceptor_memcpy (/usr/lib64/libasan.so.6.0.0+0x3c99f)
    #1 0x7fd570d10528 in u_upload_data ../src/gallium/auxiliary/util/u_upload_mgr.c:333
    #2 0x7fd57114142b in r300_upload_index_buffer ../src/gallium/drivers/r300/r300_screen_buffer.c:44
    #3 0x7fd57113943c in r300_draw_elements ../src/gallium/drivers/r300/r300_render.c:632
    #4 0x7fd57113bbc4 in r300_draw_vbo ../src/gallium/drivers/r300/r300_render.c:840
    #5 0x7fd570d212e2 in u_vbuf_draw_vbo ../src/gallium/auxiliary/util/u_vbuf.c:1487
    #6 0x7fd56fceb873 in _mesa_validated_drawrangeelements ../src/mesa/main/draw.c:1709
    #7 0x7fd56fcf28c5 in _mesa_DrawElementsBaseVertex ../src/mesa/main/draw.c:1852

Fixes: 330d0607ed ("gallium: remove pipe_index_buffer and set_index_buffer")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28523>
2024-04-12 05:05:27 +00:00
Timothy Arceri
9e056fc962 glsl: remove now unused do_dead_functions()
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28690>
2024-04-12 12:17:31 +10:00
Timothy Arceri
875ca9ec11 glsl: move validate_{stage}_shader_executable() to the nir linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28690>
2024-04-12 12:17:31 +10:00
Timothy Arceri
316165afec glsl: use info from shader when linking
We update the program copy of info at the end of linking. During linking
we should use the shader copy. This change is required to avoid updating
both in the following patch.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28690>
2024-04-12 12:15:48 +10:00
Timothy Arceri
38398cc6bb glsl: use shader info to store gs verts
Rather than passing this value around we can just store it directly
in its final location.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28690>
2024-04-12 12:15:48 +10:00
Timothy Arceri
0dcbd8a8a4 glsl: move cross_validate_uniforms() to the nir linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28690>
2024-04-12 12:15:48 +10:00
Timothy Arceri
0d8ee7534e glsl: make validate_intrastage_arrays() usable across files
This will be used in the following patch.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28690>
2024-04-12 12:15:48 +10:00
Timothy Arceri
fe2e60a4d3 glsl: add some data members to nir_variable
These will be used in the following patch.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28690>
2024-04-12 12:15:48 +10:00
Timothy Arceri
344bcd1703 glsl: move mode_string() to helper
This will be used from multiple files in the following patches.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28690>
2024-04-12 12:15:48 +10:00
nyanmisaka
7d00b759f3 radeonsi/uvd_enc: update to use correct padding size
Update padding size calculation to use cropping.
Original method could result in 0 padding, which
generated unnessary noise in the encoding result.

Cc: mesa-stable
Fixes: mesa/mesa#9196

Signed-off-by: nyanmisaka <nst799610810@gmail.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28369>
2024-04-11 21:49:54 +00:00
Sagar Ghuge
0aa632b519 anv: Use appropriate argument format for indirect draw
If index is specified we can use the DRAWINDEXED otherwise we can simply
use DRAW argument format.

v2: (Rohan & Lionel)
- Fix the aligned_stride check

Fixes: 6d4f43f0d6 ("anv: Emit EXECUTE_INDIRECT_DRAW when available")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28658>
2024-04-11 21:26:37 +00:00
Collabora's Gfx CI Team
7e82c59fa4 Uprev Piglit to dd6f7eaf82e8dd442da28b346c236141cbcce0b1
1e631479c0...dd6f7eaf82

Reviewed-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28088>
2024-04-11 20:49:33 +00:00
Hannes Mann
f419a8be90 frontends/va: Only export one handle for contiguous planes
If the driver stores all planes contiguously in memory, only one BO
needs to be exported from vaExportSurfaceHandle. This is required
for Chromium's VaapiVideoDecoder to work on radeonsi and r600.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26165>
2024-04-11 20:14:16 +00:00
Hannes Mann
4f4c9ff68a gallium/pipe: Add contiguous planes per-surface attribute
Attribute is set when textures are created by compatible drivers, but
not when importing from DMA-BUF.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26165>
2024-04-11 20:14:15 +00:00
Mike Blumenkrantz
934188c3ca zink: block LA formats with srgb
this doesn't work correctly

fixes #7218

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28674>
2024-04-11 19:52:52 +00:00
Mike Blumenkrantz
d2507a6916 nir/lower_clip: handle scalarized io
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28308>
2024-04-11 18:57:26 +00:00
Mike Blumenkrantz
49714125d5 nir/lower_clip: surgerize for lowered io
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28308>
2024-04-11 18:57:25 +00:00
Mike Blumenkrantz
7760642d2e v3d: set use_clipdist_array=true for lower_clip?
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28308>
2024-04-11 18:57:25 +00:00
Rhys Perry
c2a467dd4b aco: remove occupancy check in dealloc_vgprs()
This didn't consider that there might be different programs using the same
SIMD.

fossil-db (navi31):
Totals from 68129 (85.81% of 79395) affected shaders:
Instrs: 23230924 -> 23388315 (+0.68%)
CodeSize: 120636544 -> 121272888 (+0.53%)
Latency: 115645106 -> 115683965 (+0.03%)
InvThroughput: 18804076 -> 18806912 (+0.02%); split: -0.00%, +0.02%
Branches: 404644 -> 407945 (+0.82%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28633>
2024-04-11 18:30:47 +00:00
Rhys Perry
9775318aa9 aco: don't include the clause in VMEM_CLAUSE_MAX_GRAB_DIST
By excluding the clause from this check, we only count the number of
instructions that we're actually moving the store across.

fossil-db (navi31):
Totals from 4409 (5.55% of 79395) affected shaders:
MaxWaves: 120234 -> 119738 (-0.41%)
Instrs: 3184513 -> 3184702 (+0.01%); split: -0.09%, +0.09%
CodeSize: 15942424 -> 15943276 (+0.01%); split: -0.07%, +0.07%
VGPRs: 248448 -> 255816 (+2.97%); split: -0.04%, +3.00%
Latency: 18841156 -> 18829451 (-0.06%); split: -0.08%, +0.02%
InvThroughput: 2549229 -> 2552042 (+0.11%); split: -0.02%, +0.13%
VClause: 67760 -> 64138 (-5.35%); split: -5.40%, +0.06%
SClause: 82921 -> 82922 (+0.00%)
Copies: 270026 -> 273399 (+1.25%); split: -0.14%, +1.39%
VALU: 1793374 -> 1796743 (+0.19%); split: -0.02%, +0.21%
VOPD: 798 -> 802 (+0.50%); split: +0.63%, -0.13%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28633>
2024-04-11 18:30:47 +00:00
Job Noorman
8d55b6155c freedreno,computerator: support initialization of buffers
The following syntax can now be used to set the initial content of
buffers:

@buf size (reg) val0, val1, ...

If the buffer is not fully initialized, remaining values will be set to
zero.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28625>
2024-04-11 15:56:54 +00:00
Juan A. Suarez Romero
b3e65c77c4 v3d: configure polygon mode when enabled
The hardware do not support setting different polygon modes for front
and back faces at the same time. In this case, unless we are culling one
of the faces, we show a warning to the user.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28675>
2024-04-11 14:44:55 +00:00
Gert Wollny
6cc119522e tsan-blacklist: surpress two race conditions in TC
They are both of no consequence

v2: fix comment

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
2024-04-11 13:52:36 +00:00
Gert Wollny
ccff97f7ba tsan-blacklist: Ignore race in get_max_abs_timeout_ns
The returned value is independent of the race, so surpress it.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
2024-04-11 13:52:36 +00:00
Gert Wollny
9e7112f4df llvmpipe: Don't emit certain debug code when TSAN is enabled
It produces race conditions and is probably not interesting when running
TSAN.

v2: use #if and define values instead of "#if defined" (Yonggang Luo)
v3: remove some leftover text
v4: drop ws changes (Yonggang Luo)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
2024-04-11 13:52:36 +00:00
Gert Wollny
7c36c4f0a4 tsan-blacklist: ignore race when reading lp_fence signalled status
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
2024-04-11 13:52:36 +00:00
Gert Wollny
7dc19d941e util/u_queue: read fence->signalled locked with TSAN
When TSAN is enabled we use standard mutexes instead of futexes. With
futexes the fence->signalled is read using an atomic operation, to best
mimic this let's protect the read with a locked mutex.

This avoids TSAN reporting a race condition (false positive with
futexes) with Zink when accessing the pipeline cache.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
2024-04-11 13:52:36 +00:00
Gert Wollny
aa347029da futex: disable futexes when compiling with tsan
Thread sanitizer doesn't support futexes, so don't use them in this case
and fall back to standard mutexes. With that we can avoid tsan reporting
a large number of false positives.

v2: use #if instead of #ifdef to test the value of the define

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
2024-04-11 13:52:36 +00:00
Gert Wollny
0d46e0e88b meson: Add blacklist when compiling with tsan
Check whether the compiler actually supports it and if
not than warn about it. Note that meson will also
suggest that one should use the build-in flag, but this
is just sloppy testing for -fsanitize, -fsanitize-blacklist
is actually not available as build-in option.

v2: define THREAD_SANITIZER to 1 or 0 (suggested by Yonggang Luo)
v3: Update comment about meson warning (Dylan Baker)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
2024-04-11 13:52:36 +00:00
Vignesh Raman
446672f9b1 ci: Implement support for replaying ANGLE restricted traces
ANGLE traces must be compiled together with binaries into binary format.
Introduce them for AMD Raven device, replaying on Vulkan (radv).

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24270>
2024-04-11 12:13:34 +00:00
Jonathan Gray
094a0a2ccb intel/dev: 0x7d45 is mtl-u not mtl-h
Ref: https://ark.intel.com/content/www/us/en/ark/products/237327/intel-core-ultra-7-processor-155u-12m-cache-up-to-4-80-ghz.html
Ref: Core Ultra Processor Datasheet, Doc. No.: 792044, Rev.: 002
Fixes: 48ff68820e ("intel/dev: Enable MTL PCI ids")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27973>
2024-04-11 10:03:40 +00:00
Jordan Justen
5238b773b4 intel/dev: Change ATS-M 0x56c2 string from 170G to 170V
Ref: bspec 44477
Ref: 9123b5d5b0
Fixes: ce900dcbb1 ("intel/dev: Add ATS-M PCI ID for Data Center GPU Flex 170G")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28687>
2024-04-11 07:38:21 +00:00
Georg Lehmann
5e6e3c7f89 nir: rename to nir_opt_16bit_tex_image
Not sure what I was thinking when I wrote this pass (probably not much),
but opt makes more sense and matches other nir passes.
Fold is usually used for constants, and this pass handles more than those.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28662>
2024-04-11 06:10:33 +00:00
Dave Airlie
16682b6054 radv/video: don't advertise timestamp bits for decode/encode
At this point I'm not sure if the queues can support timestamps.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
2024-04-11 13:40:04 +10:00
Dave Airlie
ee64a385b6 radv/video: handle encode control parameters better.
The spec clarifies different operations for the reset flags,
just clean it up to follow it better.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
2024-04-11 13:40:04 +10:00
Dave Airlie
05cd42417f radv/video: enable video encoding behind perftest flag
This probes the vcn firmware version to make sure it can support
the encode extensions properly, then uses the perf test flag if so.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
2024-04-11 13:40:02 +10:00
Dave Airlie
967e4e09de radv/video: add h265 encode support
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
2024-04-11 13:40:02 +10:00
Dave Airlie
54d499818c radv/video: add initial support for encoding with h264.
This adds the encoding infrastructure along with support for h264.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
2024-04-11 13:28:32 +10:00
Dave Airlie
800c03ffbd radv/video: add parameter patching calls.
This is just infrastucture for encoding to plug into to patch
session parameters at create time.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
2024-04-11 12:57:13 +10:00
Dave Airlie
1d74661dfd radv: add encoder queue support pieces and encoder queries.
This is just checks for events and avoiding an assert in the winsys,
and adds support for the encoder queries.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
2024-04-11 12:57:05 +10:00
Dave Airlie
f6c27bea26 radv: add direct cs emit for a dword.
This lets you write a dword at a certain location, this is needed
for the encode queues.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
2024-04-11 12:48:29 +10:00
Dave Airlie
1ce215c5a3 radv/video: export unified queue header/tail functions.
These will be used for encode as well.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
2024-04-11 12:48:26 +10:00
Dave Airlie
1e16851ab1 vulkan/video: copy the profile over for h264 encode.
This allows is to use it for encoding h264 headers.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
2024-04-11 12:48:22 +10:00
Eric Engestrom
24b6a047ee docs: add sha256sum for 24.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28680>
2024-04-11 01:32:09 +00:00
Eric Engestrom
ead2f6d7f1 docs: update calendar for 24.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28680>
2024-04-11 01:32:09 +00:00
Eric Engestrom
030473f5b2 docs: add release notes for 24.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28680>
2024-04-11 01:32:09 +00:00
Timur Kristóf
cfb8f3c1a5 radv: Clean up gathering linked I/O info.
The code is more concise now without these helpers.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28488>
2024-04-11 00:44:45 +00:00
Timur Kristóf
0e481a4adc radv: Always use fixed I/O locations for TCS outputs in VRAM.
The goal of this patch is to make the TCS->TES shader I/O
independent of assigned I/O driver locations.

Always using the unlinked approach means a larger stride when
calculating some memory addresses, but otherwise should have no
perf impact whatsoever, because this only affects how TCS
outputs are stored to VRAM, and doesn't affect how they are
stored in LDS.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28488>
2024-04-11 00:44:45 +00:00
Timur Kristóf
892ebf2040 radv: Add radv_gather_unlinked_io_mask to shader info header.
We will call this from another file.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28488>
2024-04-11 00:44:45 +00:00