Commit graph

37497 commits

Author SHA1 Message Date
Chia-I Wu
c45c889f95 virgl: fix fence fd version check
Fixes: d1a1c21e76 ("virgl: native fence fd support")

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-15 23:25:47 +00:00
Chia-I Wu
442e75071b virgl: introduce virgl_drm_fence
virgl_drm_fence can wrap either a fence fd or a virgl_hw_res.  Because a
fence fd is cheaper than a virgl_hw_res, we use it whenever it is
available.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-15 23:25:47 +00:00
Chia-I Wu
334103efbf virgl: hide fence internals from the driver
Fence fds are cheaper than resources.  We want to let winsys make the
decision and use fence fds whenever they are supported.  This commit
prepares the work.

For the moment, we create a resource _and_ a fence fd when
supports_fences is true.  This will be fixed such that we create a
resource _or_ a fence fd.  (And because of a version check bug that we
will fix later, supports_fences is actually never true).

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-15 23:25:47 +00:00
Chia-I Wu
a23c091988 virgl: handle fence_server_sync in winsys
It does not need help from the driver.  This also fixes one issue where
the fence is ignored when the transfer queue is full.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-15 23:25:47 +00:00
Roland Scheidegger
88e0bbf24a gallivm: fix bogus assert in get_indirect_index
0 is a valid value as max index, and the code handles it fine. This isn't
commonly seen, as it will only happen with array declarations of size 1.
Fixes piglit tests/shaders/complex-loop-analysis-bug.shader_test

Fixes: a3c898dc97 "gallivm: fix improper clamping of vertex index when fetching gs inputs"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110441

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-04-16 00:49:38 +02:00
Rhys Perry
6281517f3e vc4: fix build
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 5131b7a43f ('gallium: add support for formatted image loads')
2019-04-15 23:27:21 +01:00
Kenneth Graunke
0f3dc832bc iris: Fix FLUSH_EXPLICIT handling with staging buffers.
I neglected to blit the staging buffer back to the real one at
transfer_flush_region (FlushMappedBufferRange) time.
2019-04-15 14:51:01 -07:00
Kenneth Graunke
62b2ce0592 iris: Preserve all PIPE_TRANSFER flags in xfer->usage
We need to preserve PIPE_TRANSFER_FLUSH_EXPLICIT, DISCARD_RANGE, and
so on, but don't want to pass them to iris_bo_map().  So, keep them all,
but mask them off when calling map.

Chris Wilson told me to do this a long time ago and he was right.
2019-04-15 14:51:01 -07:00
Kenneth Graunke
9c52dce6a9 iris: Actually mark blorp_copy_buffer destinations as written. 2019-04-15 14:51:01 -07:00
Dylan Baker
95aefc94a9 Delete autotools
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Matt Turner <mattst88@gmail.com>
2019-04-15 13:44:29 -07:00
Marek Olšák
de0c97c817 radeonsi: enable GL_EXT_shader_image_load_formatted
no changes - the driver doesn't use the format

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-15 16:18:07 -04:00
Rhys Perry
5131b7a43f gallium: add support for formatted image loads
v3: rebase
v3: make use of u_pipe_screen_get_param_defaults

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-04-15 16:18:07 -04:00
Bas Nieuwenhuizen
af9534b9f3 ac: Move has_local_buffers disable to radeonsi.
In radv we had a separate flag to actually use it + an env option
to experimentally use it.

The common code setting has_local_buffers to false of course broke
that experimental option.

Also the "enable on APU" did not make sense for RADV as it is still
disabled by default.

Fixes: b21a4efb55 "radv/winsys: allow local BOs on APUs"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-04-15 20:39:28 +02:00
Kenneth Graunke
8bf9b7b5b6 intel: Emit 3DSTATE_VF_STATISTICS dynamically
Pipeline statistics queries should not count BLORP's rectangles.

    (23) How do operations like Clear, TexSubImage, etc. affect the
         results of the newly introduced queries?

      DISCUSSION: Implementations might require "helper" rendering
      commands be issued to implement certain operations like Clear,
      TexSubImage, etc.

      RESOLVED: They don't. Only application submitted rendering
      commands should have an effect on the results of the queries.

Piglit's arb_pipeline_statistics_query-vert_adj exposes this bug when
the driver is hacked to always perform glBufferData via a GPU staging
copy (for debugging purposes).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-04-14 19:58:04 -07:00
Karol Herbst
14531d676b nir: make nir_const_value scalar
v2: remove & operator in a couple of memsets
    add some memsets
v3: fixup lima

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)
2019-04-14 22:25:56 +02:00
Karol Herbst
606b74035e lima: use nir_src_as_float
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-04-14 22:25:56 +02:00
Alyssa Rosenzweig
1e2cb3e964 panfrost/midgard: Use shared nir_lower_viewport_transform
v2: Run before lowering I/O.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-04-14 19:16:29 +00:00
Alyssa Rosenzweig
89b02bffcb panfrost: Cleanup indexed draw handling
As part of this cleanup, we use the newly-exposed
u_vbuf_get_minmax_index, deduplicating quite a bit of bookkeeping. We
also centralize the draw_flags tracking to make this code cleaner /
futureproofed; we have already had bugs regarding this field so we might
as well get it right now.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-14 15:25:46 +00:00
Alyssa Rosenzweig
74b17b9a9f panfrost/midgard: Drop dependence on mesa/st
This was used as a workaround for uniform sizing which was fixed in
771adffe ("st: Lower uniforms in st in the...")

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-14 15:25:46 +00:00
Mauro Rossi
1af7701666 draw: fix building error in draw_gs_init()
Fixes the following building error happening with Android build system:

external/mesa/src/gallium/auxiliary/draw/draw_gs.c:740:79:
error: address of array 'draw->gs.tgsi.machine->PrimitiveOffsets' will always evaluate to 'true' [-Werror,-Wpointer-bool-conversion]
         if (!draw->gs.tgsi.machine->Primitives[i] || !draw->gs.tgsi.machine->PrimitiveOffsets)
                                                      ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~
1 error generated.

Fixes: 7720ce3 ("draw: add support to tgsi paths for geometry streams. (v2)")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-04-14 18:07:02 +10:00
Qiang Yu
b46b661f53 lima/gpir: fix alu check miss last store slot
Fixes: 92d7ca4b1c "gallium: add lima driver"
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-04-14 12:10:23 +08:00
Qiang Yu
8d91cd64aa lima/gpir: fix compile fail when two slot node
Come from glmark2-es2 jellyfish test.

Fixes: 92d7ca4b1c "gallium: add lima driver"
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-04-14 12:10:23 +08:00
Vasily Khoruzhick
fef2f10cc2 lima: add support for depth/stencil fbo attachments and textures
Hardware supports writing back Z/S buffers and sampling from them,
so add support for that.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
2019-04-14 01:16:00 +00:00
Vasily Khoruzhick
a817f0fec6 lima: use individual tile heap for each GP job.
Looks like it's somehow used by subsequent PP job, so we have to
preserve its contents until PP job is done.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
2019-04-14 01:16:00 +00:00
Eric Anholt
dc402be73e v3d: Use the new lower_to_scratch implementation for indirects on temps.
We can use the same register spilling infrastructure for our loads/stores
of indirect access of temp variables, instead of doing an if ladder.

Cuts 50% of instructions and max-temps from 2 KSP shaders in shader-db.
Also causes several other KSP shaders with large bodies and large loop
counts to not be force-unrolled.

The change was originally motivated by NOLTIS slightly modifying register
pressure in piglit temp mat4 array read/write tests, triggering register
allocation failures.
2019-04-12 16:16:58 -07:00
Eric Anholt
8a2d91e124 v3d: Detect the correct number of QPUs and use it to fix the spill size.
We were missing a * 4 even if the particular hardware matched our
assumption.
2019-04-12 15:59:31 -07:00
Eric Anholt
6b1c659825 v3d: Add Compute Shader compilation support.
While waiting for the CSD UABI to get reviewed, I keep having to rebase
the CS patch.  Just land the compiler side for now to keep it from
diverging.

For now this covers just GLES 3.1 compute shaders, not CL kernels.
2019-04-12 15:59:31 -07:00
Eric Anholt
276ec879fd v3d: Drop a note for the future about PIPE_CAP_PACKED_UNIFORMS. 2019-04-12 15:58:28 -07:00
Mateusz Krzak
f4fc2ece57 panfrost: use os_mmap and os_munmap
32-bit needs mmap64 for 64-bit offsets. We get 64-bit offsets from kernel.

Signed-off-by: Mateusz Krzak <kszaquitto@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-12 16:33:00 +00:00
Mateusz Krzak
411da8b80d panfrost: cast bo_handles pointer to uintptr_t first
Required for 64-bit kernel to interpret the pointer from 32-bit userspace.

Signed-off-by: Mateusz Krzak <kszaquitto@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-12 16:33:00 +00:00
Marek Olšák
971bc10177 radeonsi: set AC_FUNC_ATTR_READNONE for image opcodes where it was missing
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-04-12 11:34:39 -04:00
Samuel Pitoiset
fd4041987b ac: add ac_build_load_helper_invocation() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-04-12 17:30:55 +02:00
Samuel Pitoiset
590a4c8981 ac: add ac_build_ddxy_interp() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-04-12 17:30:55 +02:00
Karol Herbst
a55c7352d6 lima: add bool parameter to type_size function
Fixes: 035759b61b
       ("nir/i965/freedreno/vc4: add a bindless bool to type size functions")

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-04-12 17:08:53 +02:00
Karol Herbst
98934e6aa1 nvc0/nir: enable bindless texture
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-04-12 09:02:59 +02:00
Karol Herbst
89a81fbd98 nv50/ir/nir: add support for bindless images
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-04-12 09:02:59 +02:00
Karol Herbst
b286cdedb7 nv50/ir/nir: handle bindless texture
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-04-12 09:02:59 +02:00
Karol Herbst
4a3c04a11f glsl/nir: add support for lowering bindless images_derefs
v2: handle atomics as well
    make use of nir_rewrite_image_intrinsic
v3: remove call to nir_remove_dead_derefs
v4: (Timothy Arceri) dont actually call lowering yet

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v3)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-04-12 09:02:59 +02:00
Timothy Arceri
035759b61b nir/i965/freedreno/vc4: add a bindless bool to type size functions
This required to calculate sizes correctly when we have bindless
samplers/images.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-04-12 09:02:59 +02:00
Karol Herbst
3b2a9ffd60 nir: move brw_nir_rewrite_image_intrinsic into common code
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-04-12 09:02:59 +02:00
Icenowy Zheng
400f0bfba1 lima: lower bool to float when building shaders
Both processors of Mali Utgard are float-only, so bool are not
acceptable data type of them. Fortunately the NIR compiler
infrastructure has a lower pass to lower bool to float.

Call this lower pass to lower bool to float for both GP and PP. This
makes Glamor on Xorg server 1.20.3 at least doesn't hang when starting
gtk3-demo.

The old map of nir op bcsel is changed to fcsel, and the map of b2f32 in
PP is dropped because it's not needed now (it's originally only mapped
to ppir_op_mov).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-04-12 13:40:47 +08:00
Tomeu Vizoso
8f1c686bca panfrost: Guard against reading past end of buffer
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-12 07:12:17 +02:00
Tomeu Vizoso
c35ae93803 panfrost: split asserts in pandecode
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-12 07:11:52 +02:00
Dave Airlie
604d89c2d1 llvmpipe: fix undefined shift 1 << 31.
Pointed out by coverity.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-04-12 08:54:02 +10:00
Dave Airlie
e4ed08873b draw: fix undefined shift of (1 << 31)
Pointed out by a coverity scan.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-04-12 08:53:10 +10:00
Kenneth Graunke
4fcb749044 iris: Actually pin the scratch BO.
We were pinning it for compute shaders, and pinning it when restoring
saved buffers, but we never actually pinned it in the original batch
for VS/TCS/TES/GS/FS.

Fixes rendering in GFXBench5's Tessellation demo and a bunch of Piglit
geometry shader tests.
2019-04-11 15:03:27 -07:00
Lubomir Rintel
3dd2001993 kmsro: Extend to include armada-drm
This allows using the Marvell Armada display controllers (with the
armada drm modesetting driver) along with the render-only drivers,
such as Etnaviv on an OLPC XO-1.75 laptop.

v2:
- Add to Android.mk too

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-04-11 15:53:29 +00:00
Icenowy Zheng
a155c26a66 lima: implement blit with util_blitter
As we have already prepared for using util_blitter, use it to implement
lima_blit.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-04-11 13:45:51 +00:00
Icenowy Zheng
318ccbe7b2 lima: make lima_context_framebuffer subtype of pipe_framebuffer_state
Currently the lima driver saves the framebuffer state in its
from-scratch struct lima_context_framebuffer. However, util_blitter
requires to save framebuffer with standard struct
pipe_framebuffer_state.

Make the lima_context_framebuffer a subtype of the standard
pipe_framebuffer_state, thus the standard part can be used for
util_blitter framebuffer state saving.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-04-11 13:45:51 +00:00
Icenowy Zheng
8d27bc351f lima: add dummy set_sample_mask function
The set_sample_mask function is required in util_blitter.

Add a dummy one to make util_blitter work.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-04-11 13:45:51 +00:00