The UBO special case checked I->seg before checking the instruction
message, but atomics store I->atom_opc in the same union field. Since
BI_ATOM_OPC_AUMIN aliases BI_SEG_UBO, AUMIN atomics were skipped from
memory dependency tracking.
Only apply the UBO special case to load/store instructions so atomics are
serialized correctly.
Fixes test:
KHR-GLES31.core.shader_image_load_store.basic-allTargets-atomicCS.
Fixes: 41b39d6d5d ("pan/va: Do scoreboard analysis")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42266>
v3d_launch_grid() created the job before reading the indirect
dispatch parameters, so the zero-workgroup early-out returned without
freeing it. Create the job only once the dispatch is known to proceed,
right before its first use, so the skip path has nothing to free.
Signed-off-by: JaeHoon Lee <dlwognsdc610@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42169>
v3d_disk_cache_retrieve() returns without freeing the buffer
returned by disk_cache_get() when the blob reader overruns.
Signed-off-by: JaeHoon Lee <dlwognsdc610@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42169>
v3d_render_blit() copies untiled sources into a tiled temporary
before checking if the blitter supports the operation. The
unsupported path returned without releasing the temporary like the
regular path does at the end of the blit.
Signed-off-by: JaeHoon Lee <dlwognsdc610@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42169>
v3d_create_sampler_view() takes a reference on the texture before
setting up the view, but the shadow resource error path frees the
view without releasing it. Release the reference before bailing so
the texture reference count stays balanced.
Signed-off-by: JaeHoon Lee <dlwognsdc610@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42169>
This can reuse most of the implementation done for cmd_draw_rects, just
that the layer count needs to be passed correctly to RUN_FULLSCREEN.
Tested-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Reviewed-by: Aksel Hjerpbakk <aksel.hjerpbakk@arm.com>
Reviewed-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41732>
This implements a new function that will be used for the vk_meta paths
that call cmd_draw_rects.
Tested-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Reviewed-by: Aksel Hjerpbakk <aksel.hjerpbakk@arm.com>
Reviewed-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41732>
These changes aim to make it easier to reuse this code for implementing
a cmd_draw_rects PanVK specific function that will use RUN_FULLSCREEN.
For this we need to setup the dcd a bit differently and having separate
build functions helps a lot since we mostly want to skip checking the
dirty state and moving values into registers that are done in the
prepare_draw functions.
Tested-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Reviewed-by: Aksel Hjerpbakk <aksel.hjerpbakk@arm.com>
Reviewed-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41732>
For V14, the view mask is moved to Primitive Flags 2. Instead we have a
layer index flag in Primitive Flags but this was missed during the
initial support for V14.
Fixes: 4258888f4d ("pan/genxml: Add v14 definition")
Tested-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Reviewed-by: Aksel Hjerpbakk <aksel.hjerpbakk@arm.com>
Reviewed-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41732>
This can happen when the scheduler moves a reduce operation after the last
position export in legacy VS.
It also doesn't make sense to break here. In ancient aco history null exports
were added in the assembler just before the last exec write, but we no longer
do that.
Cc: mesa-stable
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42290>
In some cases INTEL_DEBUG=hex was not working. It was getting a
failure from gen_scan_raw_layout() if the program had been padded by a
compact nop instruction.
We add this pad instruction to make the program end on an uncompacted
instruction boundary. (Perhaps this padding is not necessary.)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42144>
Add configurable SE masks for instruction timing capture and export the selected mask in RGP metadata so hit counts match the traced shader engine coverage.
An environment variable RADV_THREAD_TRACE_INSTRUCTION_TIMING_SE_MASK is used to config SE mask. If it's not specified, all SE data are captured.
Signed-off-by: Gu, Wangfeng <Wangfeng.Gu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42264>
We were unconditionally allocating lookup maps but according to vulkan
spec, app is supposed to provide hint at AS build time and use it during
the update phase.
But Indiana jones does not follow the spec:
1) BuildSizesKHR - Mode or flags are not set
2) BuildAccelerationStructuresKHR - Mode is set to Build
3) BuildAccelerationStructures - Mode is set to UPDATE
in first phase if we return size without lookup maps (based on
MODE_UPDATE condition) then update phase breaks.
Next patch will add driconf to deal with such apps.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42282>
Turns out we can figure this out at compile time.
This allows us to remove a bunch of tracking and dynamic code.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42104>
Instead of checking if any of the fs config field is SOMETIMES, just
track if the backend ever see the intrinsic being used.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42104>
The return format with the coarse bit has a different format than the
non coarse variant, as described in ICL PRMs, Volume 9: Render Engine,
Coarse to Pixel Mapping Writeback Message (SIMD8 Message).
In particular register phases 0 & 1 are required, so we cannot use the
message with/without the bit interchangeably.
When making things more static (next commit) we get failures in tests
like :
dEQP-VK.pipeline.shader_object_linked_spirv.multisample_interpolation.offset_interpolate_at_pixel_center.137_191_1.samples_2
We probably never saw the issue because there is no test using the
interpolator with coarse pixel shading enabled and in most dynamic
cases the bit is not set so the return message has the expected
format.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42104>
We never enabled GPL on hasvk so there is no point in handling dynamic
cases, it's already dead code.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42104>
