Commit graph

12733 commits

Author SHA1 Message Date
Sagar Ghuge
7e48cbb029 intel: uncached L1 to fix memory barrier issue in RT shader
In the RT shader, if there's a executeCallableEXT() in between,
even though the called shader does nothing, the instructions before and
after the executeCallableEXT() is not properly synced.

Patch fixes:
- dEQP-VK.ray_tracing_pipeline.memguarantee.inside.rgen
- dEQP-VK.ray_tracing_pipeline.memguarantee.inside.chit
- dEQP-VK.ray_tracing_pipeline.memguarantee.inside.miss
- dEQP-VK.ray_tracing_pipeline.memguarantee.inside.call

Thank to Kevin for finding out there is a load/store issue.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31201>
2024-09-24 14:33:11 +00:00
Nanley Chery
730e83b525 anv: Require compression for fast-clears on gfx20+
In commit 44351d67f8, I needed to change some variables in a check for
compression in anv_can_fast_clear_color_view(). Instead of doing that, I
dropped the check altogether because I thought the call to
anv_layout_to_fast_clear_type() which followed right afterwards would
return ANV_FAST_CLEAR_NONE if the aux usage was ISL_AUX_USAGE_NONE.

That turned out not to be the case, due to special-casing of Xe2+. For
now, make Xe2+ more like other platforms when it comes to enabling
fast-clears. If there comes a reason to actually fast-clear with
ISL_AUX_USAGE_NONE, we can revisit this.

Fixes: 44351d67f8 ("anv: Change params of anv_can_fast_clear_color_view")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11920
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31297>
2024-09-24 13:56:02 +00:00
Mike Blumenkrantz
04709e4f7d anv: fix video profile lists
these didn't include dmabuf layout or mutable formats despite both
being supported

Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31317>
2024-09-24 11:38:48 +00:00
Lionel Landwerlin
f81dc17e7d anv: add missing pipeline instance multiplier
Fix zink/anv tests : dEQP-GLES3.functional.fbo.multiview.samples_*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11911
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31341>
2024-09-24 10:36:17 +00:00
Rohan Garg
56adf42110 intel/brw: lower math op regions for Xe2+
This helps fix:
  - dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_3.tan_frag
  - dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_2.tan_frag

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31218>
2024-09-24 09:58:28 +00:00
Caio Oliveira
e1b74407bb intel/brw: Only validate GRF boundary crossing restriction for GRFs
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31294>
2024-09-24 03:39:05 +00:00
Kenneth Graunke
878ae9708a intel/brw: Don't include sync.nop in INTEL_DEBUG instruction counts
In an earlier commit, I made us stop counting sync.nops in the shader
statistics we use for shader-db (brw_debug_log_message) and fossil-db
(stats->instructions = ...).  However, I missed adjusting the printout
for INTEL_DEBUG.

Fixes: 1497f4e0c2 ("intel/fs: Don't include sync.nop in instruction count statistics")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31311>
2024-09-24 03:12:32 +00:00
Iván Briano
2e1c278e3d anv: skip rt pipeline compile if we found all shaders
When no pipeline cache is provided by the application and we rely on the
internal one, cache hits are not counted as such.
This was causing us to return COMPILE_REQUIRED on some cases where all
shaders had been found in the cache, as well as some unnecessary extra
processing in the case that we did have to compile the pipeline.

Fixes: 1dacea10f3 ("anv: implement caching for ray tracing pipelines")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31298>
2024-09-23 19:57:53 +00:00
Iván Briano
1a45c8827b anv: free shaders on rt pipeline compile error
We have not yet added the shaders to the pipeline->shaders array at
this point. If we couldn't compile (or were asked not to) the
pipeline, we were leaking references to any shaders found in the cache.
This would manifest as an assert on device destruction:
vk_pipeline_cache_destroy: Assertion `cache->object_cache->entries == 0' failed.

Fixes: 58c9f817cb ("anv: fix pipeline executable properties with graphics libraries")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31298>
2024-09-23 19:57:53 +00:00
Lionel Landwerlin
35ea8b6cd2 brw: disable null_rt only if color output does not affect other outputs
We found out that some HW changes on Xe2 make the HW avoid reading the
blend state if we're using the null_rt bit in the extended descriptor.

Since the alpha_to_coverage bit resides in the blend state, that state
is ignored and writes are going through to the depth/stencil buffers.

Disable null_rt in the color outputs if the color outputs can affect
other outputs (through alpha_to_coverage & omask).

Fixes tests in this pattern on Xe2 :

dEQP-VK.pipeline.*.multisample.alpha_to_coverage_no_color_attachment.*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Backport-to: 24.2
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31196>
2024-09-23 15:56:02 +00:00
Lionel Landwerlin
b45ce7d43e brw: move null_rt control up a layer
We'll want to tune this setting based on other parameters.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Backport-to: 24.2
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31196>
2024-09-23 15:56:02 +00:00
Lionel Landwerlin
9b42215e0d iris: ensure null render target for specific cases
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31196>
2024-09-23 15:56:02 +00:00
Lionel Landwerlin
badb3f6301 anv: Only flush render target cache when detecting RT changes
We setup an empty render target when there are no color attachments,
which effectively makes it a different surface state. In most cases
the compiler will insert a null-rt bit in the extended descriptor
which means the RT isn't even accessed. But in some cases like
alpha-to-coverage output + depth/stencil write, we will access the
render target because using the null-rt will prevent alpha-to-coverage
from happening.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2bd304bc8f ("anv: Skip the RT flush when doing depth-only rendering.")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31196>
2024-09-23 15:56:02 +00:00
Lionel Landwerlin
fb3ae17d96 anv: fix missing tracking for alpha-to-coverage runtime changes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9926aedc96 ("anv: enable EDS3 AlphaToCoverageEnable & RasterizationSamples")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31196>
2024-09-23 15:56:01 +00:00
Nanley Chery
b3882c4488 intel: Avoid no-op calls to anv_image_clear_color
Whenever we execute a fast-clear due to LOAD_OP_CLEAR, we decrease the
number of layers to clear by one. We then enter the slow clear function
and possibly exit without clearing if the layer count is zero.
Unfortunately, we've already compiled the shader for slow clears by the
time we exit. Skip the slow clear function if there are no layers to
clear.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31167>
2024-09-20 16:34:37 +00:00
Nanley Chery
1c7fe9ad1b anv: Support fast clears in anv_CmdClearColorImage
At least two game traces make use of this path: TWWH3 and Factorio.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31167>
2024-09-20 16:34:37 +00:00
Nanley Chery
46d58583ff anv: Move exec_ccs_op and exec_mcs_op higher up
The next patch will use them in anv_CmdClearColorImage().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31167>
2024-09-20 16:34:37 +00:00
Nanley Chery
03286117ef anv: Move and rename anv_can_fast_clear_color_view
It's no longer specific to image views.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31167>
2024-09-20 16:34:36 +00:00
Nanley Chery
44351d67f8 anv: Change params of anv_can_fast_clear_color_view
Expand the scope to more than just image views.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31167>
2024-09-20 16:34:36 +00:00
José Roberto de Souza
7c01cbda6f anv: Optimize vkQueueWaitIdle() on Xe KMD
vk_common_QueueWaitIdle() creates a syncobj, does a submit with no
batch buffers what translates to execute trivial_batch_bo and then
waits for syncobj to be signaled when trivial_batch_bo finishes.

On Xe KMD on other hand we can avoid the trivial_batch_bo submission
and instead use the special DRM_IOCTL_XE_EXEC with num_batch_buffer == 0
to get a syncobj to be signaled when the last exec finish execution.
This should free a bit GPU to execute more important workloads.

This will also optimize vkDeviceWaitIdle() that calls QueueWaitIdle().

It have to fallback to vk_common_QueueWaitIdle() when queue is in
VK_QUEUE_SUBMIT_MODE_THREADED mode because vkQueueWaitIdle()
could return but there still stuff in VK/CPU submission queue.
Also it could cause use after free when resources attached to
submission are freed before it is processed, example:

   vkCreateFence() or vkCreateSemaphore()
   vkQueueSubmit() // with Fence or Semaphore created above
   vkQueueWaitIdle() // with the race it returns
   vkDestroyFence() or vkDestroySemaphore()
   // vk_queue_submit_thread_func() start to process submission above...

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30958>
2024-09-19 23:12:45 +00:00
José Roberto de Souza
2f7c9f906d intel: Split anv_xe_wait_exec_queue_idle() and move part of it to common/
Split anv_xe_wait_exec_queue_idle() into 2 functions, the first
function creates the syncobj and prepares it to be signaled when the
last workload in queue is completed.

And the second one that calls the first function, then waits for the
syncobj to be signaled and destroy the syncobj.

The main reason for that is that the first function can be reused in
Iris and a future patch will add another user, so lets share it.

No changes in behavior are expected here.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30958>
2024-09-19 23:12:44 +00:00
Tapani Pälli
b01d76027d blorp: assert that color depth is not 96 for Wa_16021021469
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31263>
2024-09-19 22:44:49 +00:00
Nanley Chery
290f3a9367 intel/isl: Disable 3D Ys/Yf miptails for CCS
We currently disable CCS if a 3D Ys/Yf surface uses miptails. However,
ISL generally configures surfaces to be compatible with compression. For
consistency, disable miptails on 3D Ys/Yf surfaces in order to allow
compression.

If drivers prefer to have a more compact layout, they can pass the
ISL_SURF_USAGE_DISABLE_AUX_BIT flag at surface creation time.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30081>
2024-09-19 20:39:59 +00:00
Nanley Chery
19ed0e1685 intel/isl: Reduce miptail slot usage to allow CCS
We currently disable CCS if a surface uses more than 11 slots in a
miptail. However, ISL generally configures surfaces to be compatible
with compression. For consistency, reduce the number of slots used in
miptails in order to allow compression.

If drivers prefer to have a more compact layout, they can pass the
ISL_SURF_USAGE_DISABLE_AUX_BIT flag at surface creation time.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30081>
2024-09-19 20:39:59 +00:00
José Roberto de Souza
89c6fa1883 anv: Fix condition to clear query pool with blorp
The comment above says it all, only when queue is not protected that
it is possible to clear query pool with blorp but it was checking
the opposite.

Fixes: d5b0526507 ("anv: propagate protected information for blorp operations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31239>
2024-09-19 17:54:24 +00:00
José Roberto de Souza
0ced5663e2 anv: Improve readbility of khr_perf_query_availability_offset() and khr_perf_query_data_offset()
No changes in behavior expected here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31239>
2024-09-19 17:54:24 +00:00
José Roberto de Souza
3d09ffde46 anv/query: Fix batch end value
This were not causing any issues but better set end to the correct
value.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31239>
2024-09-19 17:54:24 +00:00
José Roberto de Souza
ac95745dc4 anv: Add documentation to some fields in anv_query_pool
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31239>
2024-09-19 17:54:24 +00:00
Sergi Blanch Torne
213f5e9152 Uprev Piglit to e9ab30aeaed97b69868cf4d6d6a3f70f3b53c362
93b4bd2e0a...e9ab30aeae

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: David Heidelberg <david@ixit.cz>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31058>
2024-09-19 15:41:32 +00:00
Eric Engestrom
b8782c783c intel/ci: track changes to the global driver *-skips.txt files
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31253>
2024-09-19 12:20:36 +00:00
Lionel Landwerlin
ed64eccab0 brw: fix virtual register splitting to not go below physical register size
Otherwise we can end up generating invalid assembly not following
destination/source alignments requirements.

Fixes the following tests:

dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.tan_frag
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_2.tan_frag
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1.tan_frag
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_3.tan_frag

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Backport-to: 24.2
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31206>
2024-09-18 23:26:34 +00:00
Dylan Baker
ec66109c1d intel/perf: delete dead code.
The inner loop with p is dead, because n_passes_written is no longer
updated as of 56bd81ee21, so it is always
comparing a uint32_t < 0, which is never true. Since the inner loop is
dead code, the pass array is dead code, as it simply keeps writing to
element 0, and but never reads or uses it, along with all of the pass
count information.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31213>
2024-09-18 19:56:04 +00:00
José Roberto de Souza
dec5a624e9 anv: Check if vkCreateQueryPool() is being created in a supported queue
Turns out not even VK CTS was calling
vkEnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHR()
to check if queue supports query.
So here adding a explicity check in our implementation of
vkCreateQueryPool().

https://github.com/KhronosGroup/VK-GL-CTS/pull/482

Cc: 24.2 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30652>
2024-09-18 15:29:16 +00:00
José Roberto de Souza
141e7eaca7 anv: Make sure all previous vm binds are done before execute perf query pool
The query pool batch buffer or other bos could not be bound when
exec starts.

Cc: 24.2 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30652>
2024-09-18 15:29:16 +00:00
José Roberto de Souza
0a19d92ca5 anv: Add warning about mismatch between query queues
Cc: 24.2 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30652>
2024-09-18 15:29:16 +00:00
José Roberto de Souza
c5d79d533a anv: Fix context id or exec queue used to open perf stream
It was always using device->context_id what is not valid in i915 when
has_vm_control is true or when running with Xe KMD.

But anv_AcquireProfilingLockKHR() don't have the queue information so
at least for now we will only support queries in a single queue.

And for consistency doing the same in
anv_QueueSetPerformanceConfigurationINTEL() although here we have the
queue parameter but queries are only supported in render engine
so it would only expose other queues if user set some parameters.

Cc: 24.2 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30652>
2024-09-18 15:29:16 +00:00
Dylan Baker
67bcdbf4a1 hasvk: remove useless uint >= 0 check
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31214>
2024-09-17 21:16:36 +00:00
Dylan Baker
27dd9fd677 anv: remove useless uint >= 0 check
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31214>
2024-09-17 21:16:36 +00:00
Lionel Landwerlin
45377dc5c4 brw: fix vecN rebuilds
When loading a 64bit address from the push constants, we'll load a
vec2, so we need to allocate 2 GRFs and MOV each component.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11831
Fixes: 339630ab05 ("brw: enable A64 loads source rematerialization")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31010>
2024-09-17 14:22:23 +00:00
Lionel Landwerlin
c16b27f66f brw: use a builder of the size of the physical register for uniforms
Should avoid any partial write non-sense on Xe2+.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 339630ab05 ("brw: enable A64 loads source rematerialization")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31010>
2024-09-17 14:22:23 +00:00
Lionel Landwerlin
02b124846f brw: fix TGM messages to use cmask lsc opcodes
This is a restriction for TGM.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b55f7716 ("intel/brw: Switch to emitting MEMORY_*_LOGICAL opcodes")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31199>
2024-09-17 09:28:58 +00:00
Lionel Landwerlin
2159e17da0 brw: remove (load|store)_raw_intel
Those are Elk specific intrinsics.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b8f264cfe4 ("intel/brw: Handle load/stores in lsc_op_for_nir_intrinsic()")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31199>
2024-09-17 09:28:58 +00:00
Dylan Baker
3f3cb1e2fa intel/elk: delete copy constructor and copy-assignment-operator
To keep the rule-of-three. This points out that the implicit copy
operations would be dangerous when there is an explicit constructor and
destructor, since the class is holding un-managed memory.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29667>
2024-09-16 20:31:45 +00:00
Dylan Baker
5809209316 anv: enforce state->cmd_buffer is never null in emit_Simpler_shader_init_fragment
We have a couple of checks where we allow this to be NULL, but later we
unconditionally and unavoidably dereference the pointer, which means
there's no way that it ever could have been NULL. Change the assert at
the top to not allow NULL, and remove checks for it being NULL

CID: 1616544
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31156>
2024-09-16 19:16:58 +00:00
Dylan Baker
5ebdfc8813 anv: assert we don't write past the end of an array
Our array has a fixed size of 32, and we know at the start of the block
that our type_count is < 32, but in the loop we grow the block, in
theory up to 31 times. Coverity notes that, and points out we could
write off the end of the array. Add an assert in the loop to ensure we
don't, and to help Coverity out.

CID: 1615171
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31173>
2024-09-16 17:42:40 +00:00
Dylan Baker
7556521417 intel: replace (uint64_t - uint64_t) > 0 with uint64_t > uint64_t
As coverity points out, if the second uint64_t was greater than the
first (I don't think it actually can be), then the overflow would result
in the check succeeding when it shouldn't. We could cast this to an
integer type, but since we have uint64_t, we'd need int128_t for that.
Instead, replace the comparison to 0 with a direct comparison, since
that would give the correct result without potential to overflow.

CID: 1604833
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31175>
2024-09-16 17:12:17 +00:00
Rohan Garg
daea7e1651 intel/compiler: use the correct cache enum for loads and stores
Fixes: 74efde7 ('intel/brw/xehp+: Drop redundant arguments of lsc_msg_desc*()')

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30742>
2024-09-16 15:18:31 +00:00
Rohan Garg
b99fd944e8 intel/compiler: version can never be above 11 due to the previous check
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30742>
2024-09-16 15:18:31 +00:00
Dylan Baker
ed8d1d3c9b anv: if queue is NULL in vm_bind return early
In the error handling path we end up creating a vk_sync and then later
we vk_sync_wait() on it. If that wait fails somehow we'll end up calling
vk_queue_set_lost(&queue->vk, ...) which would segfault if queue is
NULL.

If we end up in this situation (no queue), return directly whatever the
backend's vm_bind function returned, propagating the error up if
necessary.

Fixes: dd5362c78a ("anv/xe: try harder when the vm_bind ioctl fails")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31048>
2024-09-13 20:17:40 +00:00
Caio Oliveira
5e47c5f94a intel/executor: Fix a couple of memory leaks in the tool
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31120>
2024-09-13 01:21:24 +00:00