Commit graph

32650 commits

Author SHA1 Message Date
Eric Anholt
e2d9ed4f39 broadcom/vc5: Fix gl_FragCoord pixel center setup.
Fixes glsl-arb-fragment-coord-conventions.
2017-10-30 13:31:15 -07:00
Eric Anholt
bacbcafec1 broadcom/vc5: Always set up 1D textures as raster order.
1D is the exception to "all V3D textures are tiled", since tiling 1D
textures would just waste memory and cache space.  This ended up being a
problem once we started actually marking 1D textures as 1D instead of 2D.
2017-10-30 13:31:15 -07:00
Eric Anholt
77c7b98ba5 broadcom/vc5: Fix GPU hang with no vertex elements used by the VS.
Like VC4, we need to at least have one element set up, but unlike VC4 it
seems we don't need to read it to keep the HW happy.  Fixes GPU hangs with
glsl-no-vertex-attribs.shader_test.
2017-10-30 13:25:45 -07:00
Mauro Rossi
7dae419aa7 Android: move drivers' symlinks to /vendor (v2)
Having moved gallium_dri.so library to /vendor/lib/dri
also symlinks need to be coherently created using TARGET_OUT_VENDOR instead of TARGET_OUT
or all non Intel drivers will not be loaded with Android N and earlier,
thus causing SurfaceFlinger SIGABRT

(v2) simplification of post install command

Fixes: c3f75d483c ("Android: move libraries to /vendor")

Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Reviewed-by: Rob Herring <robh@kernel.org> (v1)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-30 15:41:31 +00:00
Christian Gmeiner
0a23841a98 etnaviv: add ext_texture_srgb support
Following piglits are passing:
 - glean@texture_srgb
 - spec@ext_texture_srgb@fbo-srgb
 - spec@ext_texture_srgb@tex-srgb
 - spec@ext_texture_srgb@texwrap formats
 - spec@ext_texture_srgb@texwrap formats-s3tc

Btw. this enables GL 2.1 :-)

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-10-28 21:20:42 +02:00
Brian Paul
1fe4c7b2af gallium: s/unsigned/enum pipe_prim_type/
In the vbuf_render::set_primitive() functions.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-10-27 16:26:26 -06:00
Roland Scheidegger
3e4fd2d4b1 draw: don't cull tris with zero area
Culling tris with zero area seems like a great idea, but apparently with
fill mode line (and point) we're supposed to draw them, at least some tests
for some other state tracker complained otherwise.
Such tris also always seem to be back facing (not sure if this can be
inferred from anything, since in a mathematical sense it cannot really be
determined), so make sure to account for this when filling in the face
information.
(For solid tris, this is of course unnecessary, drivers will throw the tris
away later in any case.)

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-10-27 22:37:19 +02:00
Dylan Baker
f7f12780c8 meson: Add a dependency on nir_opcodes_h for freedreno
This fixes a race condition in the build.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
2017-10-27 11:30:13 -07:00
Dylan Baker
f121a669c7 meson: build gallium based osmesa
This has been tested with the osdemo from mesa-demos

v2: - Add SELinux dependency
    - fix typo GALLIUM_LLVM -> GALLIUM_LLVMPIPE

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-27 11:06:45 -07:00
Dylan Baker
06c6675560 meson: move gallium include declarations to src
These are used by non-gallium osmesa, so they need to be defined outside
of the gallium subdirectory.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-27 11:06:07 -07:00
Brian Paul
7a718667f3 gallium/os: fix align_malloc() / os_malloc_aligned() comment mix-up
os_free_aligned() is the counterpart to os_malloc_aligned().
Trivial.
2017-10-27 09:54:26 -06:00
Eric Engestrom
5d44e35a8f vc4: fix release build
Mesa's DEBUG and assert's NDEBUG are not tied to each other, so we need
to explicitly compile this code out.

Fixes: 3df7892878 "vc4: Drop reloc_count tracking for debug
       asserts on non-debug builds."
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-27 11:57:03 +01:00
Samuel Pitoiset
dd79aa4ad3 radeonsi: update hack for HTILE corruption in ARK: Survival Evolved
It appears that flushing the DB metadata is actually not sufficient
since the driver uses the new VS blit shaders. This looks quite
strange though, but it seems like we need to flush DB for fixing
the corruption.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102955
Fixes: 69ccb9dae7 (radeonsi: use new VS blit shaders (VS inputs in SGPRs)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-27 10:47:30 +02:00
Marek Olšák
3f8e3c2bd8 radeonsi: add a workaround for weird s_buffer_load_dword behavior on SI
See my LLVM patch which fixes the root cause.

Users have to apply this patch and then they have 2 choices:
- Downgrade to LLVM 5.0
- Update to LLVM git after my LLVM patch is pushed.

It won't be possible to use current and earlier development version
of LLVM 6.0.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: 17.3 <mesa-stable@lists.freedesktop.org>
2017-10-26 16:44:01 +02:00
Greg V
cece4ff6a3 winsys/svga/drm: add ERESTART define for *BSD
Obtained from: FreeBSD ports

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-10-26 15:11:38 +01:00
Rob Clark
4f0f80776f freedreno: implement pipe->invalidate_resource()
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-26 08:39:32 -04:00
Rob Clark
9fc7de827e freedreno: GL_ARB_texture_barrier
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-26 08:39:32 -04:00
Rob Clark
a6bd23e43b freedreno/a5xx: rename invalidate_resource()
This is different from pipe->invalidate_resource()..

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-26 08:39:32 -04:00
Rob Clark
4afcadbcc2 freedreno/a5xx: mem2gmem is read-only for BO
This should be OUT_RELOC() since the operation isn't writing to the
buffer.  Technically it doesn't matter much currently, since we'd
anyways to a gmem2mem later.  But that will change.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-26 08:39:32 -04:00
Rob Clark
a4744c2ae7 freedreno: small rename
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-26 08:39:32 -04:00
Leo Liu
ea3dc75d72 radeon/video: add gfx9 offsets when rejoin the video surface
For CPU access.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-10-26 08:30:21 -04:00
Dave Airlie
82d47b9d38 ac/llvm: consolidate find lsb function.
This was the same between si and ac.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 15:59:31 +10:00
Dave Airlie
f925f5b074 ac/nir: move lds declaration/load/store into shared code.
This was duplicated between both drivers, share here.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 15:59:11 +10:00
Jan Vesely
a6d38f476b clover: Fix compilation after clang r315871
v2: use a more generic compat function
v3: rename and formatting cleanup

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103388
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
CC: <mesa-stable@lists.freedesktop.org>
2017-10-25 18:57:42 -04:00
Roland Scheidegger
20c77ae639 gallium/util: remove some block alignment assertions
These assertions were revisited a couple of times in the past, and they
still weren't quite right.
The problem I was seeing (with some other state tracker) was a copy between
two 512x512 s3tc textures, but from mip level 0 to mip level 8. Therefore,
the destination has only size 2x2 (not a full block), so the box width/height
was only 2, causing the assertion to trigger for src alignment.
As far as I can tell, such a copy is completely legal, and because a correct
assertion would get ridiculously complicated just get rid of it for good.

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-10-25 19:52:24 +02:00
Rob Clark
4aa69cc425 meson: build freedreno
Mostly copy/pasta from Dylan Baker's conversion of nouveau and i965.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2017-10-24 15:33:40 -04:00
Rob Clark
0ca8d53215 freedreno/ir3: use a flag instead of setting PYTHONPATH
Similar to 848da66222, pass an arg to
ir3_nir_trig.py to add to python path, rather than using $PYTHONPATH,
to prep for meson build support.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2017-10-24 15:33:40 -04:00
Rob Clark
eed9685dd6 freedreno: per-context fd_pipe
To enable per-context priorities, we need to have per-context pipe's.
Unfortunately we still need to keep the global screen pipe, mostly just
for screen->get_timestamp().

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-24 12:56:51 -04:00
Rob Clark
9c32333a58 freedreno: rename pipe -> vsc_pipe
To add context priority support we need to have an fd_pipe per context,
rather than per-screen.  Which conflicts with existing ctx->pipe (which
is actually a visibility stream pipe (hw resource).  So just rename it.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-24 12:56:51 -04:00
Rob Clark
7e7096307a freedreno: pass context flags through to fd_context_init()
Prep work for later patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-24 12:56:51 -04:00
Brian Paul
7a6c6e73a8 gallium/util: use util_snprintf() in u_socket_connect()
Instead of plain snprintf().  To fix the MSVC build.

snprintf() is used in various places in Mesa/gallium, but apparently,
not in code built with MSVC.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-24 08:17:15 -06:00
Marek Olšák
2a414c3961 radeonsi: postponed KILL isn't postponed anymore, but maintains WQM
This restores performance for the drirc workaround, i.e.
KILL_IF does:
   visible = src0 >= 0;
   kill_flag &= visible; // accumulate kills
   amdgcn_kill(wqm_vote(visible)); // kill fully dead quads only

And all helper pixels are killed at the end of the shader:
   amdgcn_kill(kill_flag);

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-24 14:56:34 +02:00
Marek Olšák
da0083f123 radeonsi: use postponed KILL only when derivatives are used
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-24 14:56:34 +02:00
Marek Olšák
1ff9e27cbd ac: replace ac_build_kill with ac_build_kill_if_false
This will be a new LLVM intrinsic and will also work nicely with
llvm.amdgcn.wqm.vote.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-24 14:56:34 +02:00
Brian Paul
069211f205 gallium/util: don't call close() on Windows in u_tests.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-23 15:10:44 -06:00
Brian Paul
5134c0dedf mesa: use util_strdup() macro in u_debug_symbol.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-23 15:10:38 -06:00
Brian Paul
6230773936 gallium/util: replace gethostbyname() with getaddrinfo()
Compiling with MSVC options /we4995 /we4996 (a subset of /sdl) generates
a warning that the gethostbyname() function is deprecated in favor of
getaddrinfo() or GetAddrInfoW().  Replace the call with getaddrinfo().

Untested.  There are no callers to u_socket_connect() in Gallium.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-23 15:10:01 -06:00
Dylan Baker
d4567efa5c meson: build imx driver
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-10-23 11:45:55 -07:00
Dylan Baker
51558a1d6c meson: build etnaviv driver + winsys
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-10-23 11:45:38 -07:00
Bas Nieuwenhuizen
a548b727a1 ac/nir: Only clamp shadow reference on radeonsi.
Vulkan CTS does not expect the value to be clamped (at least for D32),
and it makes a differences even though depth is in [0,1], due
to strict inequalities.

I couldn't find anything in the Vulkan spec about this, but the test
seemed to be copied from GL tests and the GL spec only specifies
clamping for fixed point formats. Hence I expect radeonsi to run into
this at some point as well, but given that they still have a usecase
with the Z16->Z32 promotion, I'll leave that for someone else to clean
up.

This at least fixes radv dEQP-VK.texture.shadow.* on VI.

Fixes: 0f9e32519b 'ac/nir: clamp shadow texture comparison value on VI'
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-23 09:13:38 +02:00
Stefan Schake
e5fea0d621 broadcom/vc4: Fix aliasing issue
This was causing Android clang version 3.8.256229 to miscompile,
presumably due to strict aliasing.

Fixes: 14dc281c13 ("vc4: Enforce one-uniform-per-instruction after optimization.")
2017-10-20 17:09:35 -07:00
Andres Rodriguez
557de3b9ae radeonsi: hardcode shader WAVE_LIMIT to the maximum value
This is part of a cooperative scheduling approach used by radv. All
drivers in the stack must opt-in to resource arbitration, otherwise GL
based apps will be able to ignore system priorities.

We always hardcode the field to its maximum value, instead of attempting
to calculate an approximate usage. In testing, there were no benefits to
using anything other than the maximum.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21 01:01:44 +02:00
Eric Anholt
0e6fee7328 broadcom/vc5: Fix pasteo that broke vertex texturing.
We weren't ever filling in the texture state record, so we'd dereference
NULL from the shader.
2017-10-20 15:59:41 -07:00
Eric Anholt
34690536a7 broadcom/vc5: Move default attribute value setup to the CSO and fix them.
I was generating some stub values to bring the driver up, but fill them in
properly now.  We now set 1.0 or 1u as appropriate, and thanks to being in
their own BO it fixes piglit failures on the 7268 (where our 4-byte
alignment was insufficient).

Fixes const-packHalf2x16.shader_test
2017-10-20 15:59:41 -07:00
Eric Anholt
fb15168919 broadcom/vc5: Move most of the shader state attribute record to the CSO.
This should reduce our draw-time overhead, and puts the code where it
should go long term.
2017-10-20 15:53:55 -07:00
Eric Anholt
f4ff8f74ee broadcom/vc5: Fix build failure frm nir_shader::stage removal.
Fixes: 59fb59ad54 ("nir: Get rid of nir_shader::stage")
2017-10-20 15:53:55 -07:00
Jason Ekstrand
59fb59ad54 nir: Get rid of nir_shader::stage
It's redundant with nir_shader::info::stage.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-10-20 12:49:17 -07:00
Christian Gmeiner
65ccee2dc2 etnaviv: fix implicit conversion warning
Galliums query_type used in APIs is unsigned.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-10-20 12:42:55 +02:00
Christian Gmeiner
57a586828f etnaviv: enable occlusion query if GPU supports it
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-10-20 12:42:48 +02:00
Christian Gmeiner
246243d447 etnaviv: add support for occlusion queries
Passes most occlusion query piglits. The following piglits are broken:
- spec@arb_occlusion_query@occlusion_query_meta_fragments
- spec@arb_occlusion_query@occlusion_query_meta_save
- spec@arb_occlusion_query2@render

v1 -> v2:
 - use one sample provider for all occlusion queries tyes
 - add comment about 'magic' value 0x1DF5E76

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-10-20 12:42:44 +02:00