Commit graph

20211 commits

Author SHA1 Message Date
Christian Gmeiner
b8c335c91b etnaviv: update headers from rnndb
Update to etna_viv commit 6c9c706.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-10-20 12:42:35 +02:00
George Kyriazis
f9d239e11f swr: Rework scratch space allocation
Remove allocation of > 2kbyte buffers into context memory in
swr_copy_to_scatch_space() (which is used to copy small vertex/index buffers
and shader constants to a scratch space to be used by the upcoming draw.)

Large shader constant allocations need to be done in the circular scratch
buffer instead of context memory, because their values persist across
render calls.

Also lower SCRATCH_SINGLE_ALLOCATION_LIMIT to 8k, since allocations of larger
buffers will get too large for the circular scratch space.

Fixes render issues with CEI Ensight.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-19 20:18:09 -05:00
Tim Rowley
bfda35c8dd swr: knob overrides for Intel Xeon Phi
Architecture benefits from having more threads/work outstanding.

Patch by Jan Zielinski.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-19 13:10:55 -05:00
Tim Rowley
028ffa5e18 swr/rast: Add api to override draws in flight
Allow draws in flight to be overridden via SWR_CREATECONTEXT_INFO.

Patch by Jan Zielinski.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-19 13:10:55 -05:00
Tim Rowley
2559f2b93e swr/rast: Widen fetch shader to SIMD16 (disabled for now)
Refactored the gather operation to process 16 elements at a time via
paired SIMD8 operations.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-19 13:10:55 -05:00
Tim Rowley
49090ccf54 swr/rast: Change DS memory allocation
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-19 13:10:55 -05:00
Tim Rowley
04ea03d99d swr/rast: Fix indentation
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-19 13:10:55 -05:00
Tim Rowley
62e2d657c8 swr/rast: Miscellaneous viewport array code changes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-19 13:10:55 -05:00
Tim Rowley
ed1db803fa swr/rast: Minor changes for os-x
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-19 13:10:55 -05:00
Roland Scheidegger
3d0deed12a llvmpipe: handle shader sample mask output
This probably isn't all that useful for GL, but there are apis where
sample_mask is a valid output even without msaa.
Just discard the pixel if the sample_mask doesn't include the bit for
sample 0.

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-10-18 18:16:44 +02:00
Eric Anholt
4f3e380fa0 meson: Add support for the vc5 driver.
v2: Default vc5 to off, since it requires the simulator currently.  Add
    missing dep on the XML generation from libbroadcom_vc5.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com> (v1)
2017-10-17 13:41:59 -07:00
Eric Anholt
1ae8018a6a meson: Add support for the vc4 driver.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2017-10-17 13:41:59 -07:00
Marek Olšák
2f4705afde radeonsi: if there's just const buffer 0, set it in place of CONST/SSBO pointer
SI_SGPR_CONST_AND_SHADER_BUFFERS now contains the pointer to const buffer 0
if there is no other buffer there.

Benefits:
- there is no constbuf descriptor upload and shader load

It's assumed that all constant addresses are within bounds. Non-constant
addresses are clamped against the last declared CONST variable.
This only works if the state tracker ensures the bound constant buffer
matches what the shader needs.

Once we get 32-bit pointers, we can only do this for user constant buffers
where the driver is in charge of the upload so that it can guarantee a 32-bit
address.

The real performance benefit might not be measurable.

These apps get 100% theoretical benefit in all shaders (except where noted):
- antichamber
- barman arkham origins
- borderlands 2
- borderlands pre-sequel
- brutal legend
- civilization BE
- CS:GO
- deadcore
- dota 2 -- most shaders
- europa universalis
- grid autosport -- most shaders
- left 4 dead 2
- legend of grimrock
- life is strange
- payday 2
- portal
- rocket league
- serious sam 3 bfe
- talos principle
- team fortress 2
- thea
- unigine heaven
- unigine valley -- also sanctuary and tropics
- wasteland 2
- xcom: enemy unknown & enemy within
- tesseract
- unity (engine)

Changed stats only:
    SGPRS: 2059998 -> 2086238 (1.27 %)
    VGPRS: 1626888 -> 1626904 (0.00 %)
    Spilled SGPRs: 7902 -> 7865 (-0.47 %)
    Code Size: 60924520 -> 60982660 (0.10 %) bytes
    Max Waves: 374539 -> 374526 (-0.00 %)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
854593b8eb ac: clean up ac_build_indexed_load function interfaces
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
cdb21dfffa radeonsi: handle 64-bit loads earlier in fetch_constant
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
ee0e1a47ce radeonsi: add si_descriptors::gpu_address and remove buffer_offset
This allows us to change the pointer arbitrarily.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
6d2664880c radeonsi: unify code for extracting a buffer address from a descriptor
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
8d2685d129 radeonsi: remove atom parameter from si_upload_descriptors
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
4ddce1b1a4 radeonsi: pack si_descriptors better again
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
859eeffb3d radeonsi: emit dirty consecutive pointers in one SET_SH_REG packet
IB size: -1.6%

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
36626ffe46 radeonsi: split si_emit_shader_pointer
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
69325fa88d radeonsi: generalize the SI_VS_SHADER_POINTER_MASK macro
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
79c2e7388c radeonsi/gfx9: use SPI_SHADER_USER_DATA_COMMON
IB size: -0.4%

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
b762a08896 radeonsi/gfx9: move RW_BUFFERS from s[0:1] to s[8:9] for HS and GS
Let's use the same user data SGPRs in all stages.
(for SPI_SHADER_USER_DATA_COMMON_0)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Marek Olšák
0aafedbbb2 radeonsi: add GFX-IB-size query to the HUD
It shows the sum of all IBs per frame.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-17 22:03:03 +02:00
Eric Anholt
cde209960c broadcom/vc4: Fix false-positive for the tiling ioctls on simulator mode.
If there happened to be an ENOENT laying around, we would try using the
ioctls later and fail out resource allocation.
2017-10-17 12:35:16 -07:00
Eric Anholt
b202f90f65 broadcom/vc4: Skip BO labeling when in simulator mode.
It was calling down into i915 trying to label the BO, which is definitely
not the right thing.
2017-10-17 12:35:16 -07:00
Eric Anholt
d623a34ab2 broadcom/vc5: Don't forget to set the RT format for 1555 textures.
Fixes dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.rgb5_a1
2017-10-17 12:35:16 -07:00
Dylan Baker
6a9ad20b7c meson: build llvmpipe
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
de24d61765 meson: build softpipe
This doesn't include llvmpipe.

v2: - Fix inconsistent use of with_gallium_swrast and
      with_gallium_softpipe.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
813b4b09f9 meson: build nouveau (gallium) driver
Tested with a GK107.

v2: - Add target for nouveau standalone compiler. This target is not
      built by default.
v3: - Add nouveau to list of drivers built by default

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
b154b44ae3 meson: build radeonsi gallium driver
This hooks up the bits necessary to build gallium dri drivers, with
radeonSI as the first example driver. This isn't tested yet.

v4: - drop radeonsi generated header from sources.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
66f97f6640 meson: build radeonsi
This builds the radeonsi (and radeon) window system bits and gallium
driver bits.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
4d701ee969 meson: build gallium helper drivers
This builds ddebug, noop, rbug, and trace drivers.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
2017-10-16 16:32:43 -07:00
Eric Engestrom
b05820621d svga: format the version string like the rest of mesa
All 4 other version strings do it like this.
((Also, double parentheses just look confusing))

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-10-16 18:52:41 +01:00
Brian Paul
4542a63254 svga: fix format_conversion_table breakage
The new A1B5G5R5_UNORM, X1B5G5R5_UNORM formats were added in the
wrong place in commit ef874ee450.

Fixes: ef874ee450 "gallium: Add support for 5551 with the 1-bit field in the low bit."

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-16 10:58:02 -06:00
Ilia Mirkin
790b5c4a38 a2xx: add support for a few 16-bit color rendering formats
The rest should be possible too, just needs some additional
investigation. Passes fbo-*-formats piglit tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-10-15 12:09:21 -04:00
Wladimir J. van der Laan
d3af7f5153 freedreno/a20x: Enable rendering to RGBA/RGBX
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-10-15 12:09:14 -04:00
Wladimir J. van der Laan
c10eeb454d freedreno/a20x: Fix rendering to BGRX
Make sure that BGRX rendering is swapped the correct way around.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-10-15 12:09:03 -04:00
Lucas Stach
4daee6733f etnaviv: rework TS enable to be a derived state
Draw operations should not use the TS if the TS buffer content is invalid,
as this leads to wrong rendering or even GPU hangs. As the TS valid status
can change between draws (clear operations changing it to valid, blits using
the RS to the color or ZS buffer changing it to invalid), the TS_MEM_CONFIG
must be updated before each draw if the status has changed.

This fixes the remaining TS related piglit failures (regressions of a
standard run against a piglit run with TS completely disabled).

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-10-14 16:40:08 +02:00
Lucas Stach
34360ac6ed etnaviv: skip unused vertex attributes when assigning VS inputs
When not all of the vertex attributes are actually used in the shader,
we end up with some inputs without an assigned reg. Those are marked
as invalid and must be skipped when assigning the inputs, as those would
overwrite other valid inputs otherwise.

Fixes piglit drawpixels and a bunch of other tests using the st_draw path.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-10-14 16:39:46 +02:00
Eric Anholt
dbf9e4fbf8 broadcom/vc5: Remove the u_resource_vtbl usage.
Like for vc4, this was just a wasted indirection.
2017-10-12 12:44:27 -07:00
Marek Olšák
f536f45250 radeonsi: implement sync_file import/export
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 21:07:48 +02:00
Marek Olšák
162502370c winsys/amdgpu: implement sync_file import/export
syncobj is used internally for interactions with command submission.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 21:07:41 +02:00
Marek Olšák
11adea4b24 ac: add radeon_info::has_sync_file
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 21:04:56 +02:00
Marek Olšák
07fdc0a09c gallium: add pipe_screen::check_resource_capability
This is optional (and no CAP).

Implemented by radeonsi, ddebug, rbug, trace.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
Wladimir J. van der Laan
78ade65956 etnaviv: Do GC3000 resolve-in-place when possible
If an RS blit is done with source exactly the same as destination, and
the hardware supports this, do an in-place resolve. This only fills in
tiles that have not been rendered to using information from the TS.

This is the same as the blob does and potentially saves significant
bandwidth when doing i.MX6qp scanout using PRE, and when rendering to
textures (though here using sampler TS would be even better).

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2017-10-12 16:03:26 +02:00
Nicolai Hähnle
bc2d874101 radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORM
Fixes dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-12 08:42:55 +02:00
Tim Rowley
e484805352 swr: simd16 shaders work in progress
Start building vertex shaders as simd16.

Disabled by default, set USE_SIMD16_SHADERS in knobs.h to experiment.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-11 14:35:23 -05:00
Ilia Mirkin
b20bccbcac nv50,nvc0: fix push hint logic in presence of a start offset
Previously buffer offsets were passed in explicitly as an offset, which
had to be added to the resource address. Now they are passed in via an
increased 'start' parameter. As a result, we were double-adding the
start offset in this kind of situation.

This condition was triggered by piglit's draw-elements test which has a
requisite glMultiDrawElements in combination with a small enough number
of vertices to go through the immediate push path.

Fixes: 330d0607ed ("gallium: remove pipe_index_buffer and set_index_buffer")
Reported-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2017-10-11 08:18:16 -04:00