Commit graph

17695 commits

Author SHA1 Message Date
Rhys Perry
b70ecfa588 aco: only join barrier_imm/barrier_events for logical edges
fossil-db (gfx1201):
Totals from 3 (0.00% of 79653) affected shaders:
Instrs: 2904 -> 2893 (-0.38%)
CodeSize: 14944 -> 14900 (-0.29%)
Latency: 14703 -> 14248 (-3.09%)
InvThroughput: 1237 -> 1210 (-2.18%)

fossil-db (navi31):
Totals from 3 (0.00% of 79653) affected shaders:
Instrs: 2742 -> 2731 (-0.40%)
CodeSize: 14136 -> 14092 (-0.31%)
Latency: 14744 -> 14287 (-3.10%)
InvThroughput: 1241 -> 1213 (-2.26%)

fossil-db (navi21):
Totals from 3 (0.00% of 79653) affected shaders:
Instrs: 2326 -> 2315 (-0.47%)
CodeSize: 12472 -> 12428 (-0.35%)
Latency: 14921 -> 14465 (-3.06%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>
2025-06-06 11:51:08 +01:00
Rhys Perry
62a9b4b976 aco: set vmem_types for args_pending_vmem
fossil-db (gfx1201):
Totals from 0 (0.00% of 79653) affected shaders:

fossil-db (navi31):
Totals from 11 (0.01% of 79653) affected shaders:
Instrs: 4543 -> 4554 (+0.24%)
CodeSize: 23256 -> 23300 (+0.19%)

fossil-db (navi21):
Totals from 8 (0.01% of 79653) affected shaders:
Instrs: 2333 -> 2341 (+0.34%)
CodeSize: 12328 -> 12360 (+0.26%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.0
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>
2025-06-06 11:51:08 +01:00
Samuel Pitoiset
babeb975c4 radv,radeonsi: fix emitting UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12
Some checks are pending
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Not all PFP firmwares for GFX12 have this packet.

Fixes: 47f5d25f93 ("radv,radeonsi: emit UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13312
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35370>
2025-06-05 16:51:07 +00:00
Rhys Perry
00a2ed60f8 radv/meta: use unsigned min in copy/fill shaders
Otherwise, this would break >2 GiB copy/fill.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport: 25.1
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35343>
2025-06-05 09:55:32 +00:00
Georg Lehmann
297fdc6636 radv: don't accidentally expose samplerFilterMinmax through Vulkan 1.2
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35339>
2025-06-05 09:01:19 +00:00
Marek Olšák
c3034fa82c amd: replace most u_bit_consecutive* with BITFIELD_MASK/RANGE
Some checks are pending
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35346>
2025-06-04 17:46:38 +00:00
David Rosca
e579b982b0 radv/video: Set all pic params for H264 encode refs
Fixes encoding B-frames with I-frame as L1 reference.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35283>
2025-06-04 11:33:02 +00:00
David Rosca
92e99e6169 radv/video: Add radv_enc_h264/5_pic_type
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35283>
2025-06-04 11:33:02 +00:00
Samuel Pitoiset
098c15bfc9 radv: use paired shader registers for graphics on GFX12
Some checks are pending
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Loosely based on RadeonSI.

This is supposed to be faster because parsing the packet header seems
to be the main bottleneck on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35282>
2025-06-04 09:17:51 +00:00
Samuel Pitoiset
c8b3c92a3e radv: add macros for paired shader registers on GFX12
Imported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35282>
2025-06-04 09:17:51 +00:00
Samuel Pitoiset
c8f9e0fb05 radv: add a new dirty state for emitting tess user SGPRs
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35282>
2025-06-04 09:17:51 +00:00
Georg Lehmann
c27cdaac70 radv: expose scalarBlockLayout on GFX6
Scalar block layout doesn't allow anything that our memory load/store vectorizer
couldn't create on its own. So I assume whatever reason there was to only
expose this feature on GFX7+ was incorrect or ended up being fixed.

Passes vkcts in CI on tahiti.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35279>
2025-06-04 08:49:57 +00:00
Karol Herbst
4f5ce2d5aa ac/nir: fix unaligned single component load/stores
This fixes two problems:
1. we need to lower the bit_size according to the alignment.
2. num_components could end up being 0, so we need to round up instead.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13102
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34976>
2025-06-03 13:14:31 +00:00
Samuel Pitoiset
94a4ba5b4d radv/ci: bump the timeout for radv-polaris10-vkcts
Looks like it's actually also affected by the memory explosion caused
by zerovram alloc by default in AMDGPU. Though it's very random,
sometimes the job will finish in 40 minutes, sometimes it needs more
than 1h15m. Let's bump the timeout because it's a post-merge job.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35157>
2025-06-03 10:18:30 +00:00
Rhys Perry
2e82f481ca radv: fix too large shift exponent in radv_remove_color_exports
"shift exponent 1020 is too large for 32-bit type 'unsigned int'" with
madmax/25b8180e05220b8c and UBSan

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35255>
2025-06-03 09:45:01 +00:00
Valentine Burley
3a0cc0ee0d ci: Use zstd compressed kernel modules
Change how we package kernel modules: instead of storing them in
.tar.zst archives with uncompressed .ko files inside, we now compress
each .ko file individually with ZSTD and bundle them into a plain tar
archive.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35129>
2025-06-03 07:27:26 +00:00
Georg Lehmann
a6675f35b2 aco: clamp exponent of 16bit ldexp
The hw uses only a 16bit int, but NIR's src is 32bit.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34073>
2025-06-03 06:34:18 +00:00
Natalie Vock
dac6f09451 radv/rt: Report 256 byte alignment for scratch
This mirrors AMDVLK. 128-byte alignment is possible, but DOOM: The Dark
Ages screws up scratch allocation with alignments <256 bytes.

Fixes hangs in DOOM: The Dark Ages.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35152>
2025-06-02 19:52:51 +00:00
Natalie Vock
6628ac8ad9 radv/rt: Avoid encoding infinities in box node coords
On Navi33, certain box sorting modes combined with infinity/-infinity in
the child AABBs cause image_bvh64_intersect_ray to return garbage node
pointers.

To avoid this, convert infinity to the maximum representable
floating-point value, which will still intersect with any non-inf ray.

Fixes consistent hangs in DOOM: The Dark Ages.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35254>
2025-06-02 19:33:18 +00:00
Rhys Perry
1fdfdbaf92 aco/hard_clauses: simplify and complete get_type()
Some checks are pending
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
This now includes image_msaa_load and the new atomic instructions in
GFX12.

It also treats point sample accelerated MIMG as either sample or load,
like the waitcnt insertion pass. I'm not sure if that's necessary or not,
though.

No fossil-db changes (gfx1201, gfx1150 and navi31).

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35235>
2025-06-02 10:28:10 +00:00
Rhys Perry
8764ec0230 aco: consider image_msaa_load a sample operation before gfx12
LLVM commit 62dea99a7d7df9daedbb86133f3d46699cd2728d made this instruction
a sample for all GFX levels, then with f898161bfa95723954a273a519180e070a5ccd2e
it was changed to be GFX12+. Now 34b6285735c999d2fab77b0ff8e5b497d86df3af
changed it to be all GFX levels again.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35235>
2025-06-02 10:28:09 +00:00
David Rosca
960f63596f radv/video: Add VCN5 encode support
Some checks are pending
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New with VCN5 is separate reference images support.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35261>
2025-06-02 09:30:30 +00:00
David Rosca
4a3b3febda radv/video: Enable decode on VCN5
No differences from VCN4 for tier2.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13118
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35261>
2025-06-02 09:30:30 +00:00
David Rosca
25f7996395 radv/video: Set correct minCodedExtent for encode
Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35261>
2025-06-02 09:30:30 +00:00
David Rosca
ef305f3875 radv: Use RADEON_SURF_VIDEO_REFERENCE for video DPB images
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35261>
2025-06-02 09:30:30 +00:00
Samuel Pitoiset
47f5d25f93 radv,radeonsi: emit UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12
Some checks are pending
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This try to mitigate the HiZ GPU hang by increasing a timeout. Loosely
based on PAL but I can confirm it delays the hang when
BOTTOM_OF_PIPE_TS is used as a workaround.

This must be emitted when the GFX queue is idle.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35212>
2025-06-02 07:30:18 +00:00
David Rosca
8f4e251c98 radeonsi/vcn: Support disabling HEVC dependent slice segments
With older FW this needs to be always enabled, but it can now be
disabled when using the new separate header instructions for
dependent_slice_segment_flag and slice_segment_address.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35072>
2025-05-30 08:29:53 +00:00
Samuel Pitoiset
9692ef41a3 aco: implement bitfield_extract for 8-bit/16-bit
Some checks are pending
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35199>
2025-05-29 12:24:59 +00:00
Samuel Pitoiset
fe2c93a788 ac/nir: enable 64-bit lowering for bitfield_extract
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35187>
2025-05-29 08:45:41 +02:00
Samuel Pitoiset
8596150ae8 aco: implement bitfield_reverse for types other than 32-bits
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34583>
2025-05-28 09:52:12 +00:00
Daniel Schürmann
5b4d284493 aco/isel: use vector-aligned operands for image_bvh64_intersect_ray
Totals from 93 (0.12% of 79377) affected shaders: (Navi48)
MaxWaves: 1376 -> 1368 (-0.58%)
Instrs: 3583500 -> 3581861 (-0.05%); split: -0.05%, +0.00%
CodeSize: 18792300 -> 18785296 (-0.04%); split: -0.04%, +0.00%
VGPRs: 8652 -> 8592 (-0.69%); split: -1.25%, +0.55%
Latency: 20861347 -> 20834407 (-0.13%); split: -0.17%, +0.04%
InvThroughput: 4032604 -> 4028020 (-0.11%); split: -0.14%, +0.03%
VClause: 90507 -> 90525 (+0.02%); split: -0.01%, +0.03%
Copies: 279429 -> 277839 (-0.57%); split: -0.58%, +0.01%
Branches: 100260 -> 100251 (-0.01%)
PreVGPRs: 8949 -> 8771 (-1.99%)
VALU: 1955635 -> 1954053 (-0.08%); split: -0.08%, +0.00%
SALU: 477347 -> 477329 (-0.00%); split: -0.01%, +0.01%
VOPD: 69 -> 61 (-11.59%)

Totals from 93 (0.12% of 79377) affected shaders: (Navi31)

MaxWaves: 1376 -> 1374 (-0.15%)
Instrs: 3442606 -> 3440344 (-0.07%); split: -0.07%, +0.00%
CodeSize: 17801008 -> 17790476 (-0.06%); split: -0.07%, +0.01%
VGPRs: 8652 -> 8556 (-1.11%); split: -1.25%, +0.14%
Latency: 20590943 -> 20542279 (-0.24%); split: -0.27%, +0.03%
InvThroughput: 3978133 -> 3969497 (-0.22%); split: -0.25%, +0.03%
VClause: 91784 -> 91769 (-0.02%); split: -0.05%, +0.03%
Copies: 277177 -> 275263 (-0.69%); split: -0.70%, +0.01%
Branches: 100098 -> 100092 (-0.01%); split: -0.02%, +0.01%
PreVGPRs: 9021 -> 8843 (-1.97%)
VALU: 2001794 -> 1999893 (-0.09%); split: -0.10%, +0.00%
SALU: 419504 -> 419559 (+0.01%); split: -0.01%, +0.02%
VOPD: 77 -> 64 (-16.88%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:17 +00:00
Rhys Perry
c50f9541e4 aco/tests: Add tests for vector-aligned operands
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:17 +00:00
Daniel Schürmann
b5382faa9c aco/validate: validate register assignment of vector-aligned operands
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:17 +00:00
Daniel Schürmann
9091c3bf5b aco/ra: add affinities for MIMG vector-aligned operands
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:17 +00:00
Daniel Schürmann
fb689f133e aco/ra: handle register assignment of vector-aligned operands
Vector-aligned operands are handled by temporarily allocating
a vector-SSA value for the duration of the instruction.
On completion of the register assignment, the individual
operands are assigned to the reserved register space and,
if necessary, parallelcopies are emitted.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:17 +00:00
Daniel Schürmann
92b1154397 aco/ra: Always rename copy-kill operands, even if the temporary doesn't match
This makes it independent of whether the operand already got renamed or not.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:17 +00:00
Daniel Schürmann
4fad3514a9 aco/ra: only change registers of already handled operands in update_renames()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:17 +00:00
Daniel Schürmann
51a2e1eb94 aco/ra: don't use kill-flags as indicator in get_reg_create_vector()
We are about to re-use this function for vector-aligned operands.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:17 +00:00
Daniel Schürmann
3d8b355f22 aco/assembler: support vector-aligned operands on MIMG instructions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:17 +00:00
Daniel Schürmann
8cb1700c74 aco/print_ir: print parenthesis around vector-aligned operands
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:16 +00:00
Daniel Schürmann
6aabcb02a1 aco/print_ir: only print 'lateKill' if requested via print_kill flag
Also only print lateKill for actually killed operands.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:16 +00:00
Daniel Schürmann
a9645fdd89 aco: introduce concept of vector-aligned Operands
Operand::isVectorAligned indicates that the Operand is part of a vector
consisting of multiple operands. Therefore, it must reside in a register
aligned with the next Operand.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:16 +00:00
Daniel Schürmann
a4fa3935fd aco/live_var_analysis: set same lateKill flags for same operands
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:16 +00:00
Daniel Schürmann
ee0ee282b9 aco: simplify Operand() constructor
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34359>
2025-05-28 09:24:16 +00:00
Samuel Pitoiset
2ebfa64be7 radv: add radv_disable_hiz_his_gfx12 and enable for Mafia Definitive Edition
Some checks are pending
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This is a workaround for random GPU hangs with HiZ/HiS on GFX12
because the correct fix is complex and it will take time to be
implemented properly.

Mafia Definitive Edition is the first known game affected by this.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13222
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35182>
2025-05-28 07:20:26 +00:00
Samuel Pitoiset
63758bc093 radv: fix capture/replay with sparse images and descriptor buffer
Some checks are pending
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The sparse image VA needs to be returned to the application for replay.

Reported by Baldur.

VKCTS has coverage but it doesn't verify this yet.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35162>
2025-05-27 19:30:18 +00:00
Yogesh Mohan Marimuthu
1af419deed ac: for userq do not set info->has_fw_based_shadowing
register shadow enabling for user queue is different code flow than
kernel queue. In case of kernel queue preamble ib is initialized which
is not requried for kernel queue.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34803>
2025-05-27 14:25:50 +00:00
Yogesh Mohan Marimuthu
137907945f ac: add AMD_USERQ env var to enable user queue
user queue is enabled only if AMD_USERQ env var is set and Kernel
supports user queue.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34803>
2025-05-27 14:25:50 +00:00
Yogesh Mohan Marimuthu
97c48c5aa7 ac: fix getting mcbp info for userq
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34803>
2025-05-27 14:25:50 +00:00
Samuel Pitoiset
69467f26c9 radv/ci: remove RADV_PERFTEST=video_{decode,encode} when it's the default
It's automatically enabled when recent kernels.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34879>
2025-05-27 08:47:50 +00:00