This instruction is used to implement float type conversion. The source type
is defined via src1 immed (0: f32, 1: f16) and the dest type is defined via
the instruction type.
Blob generates such conv's for piglit's tests/cl/program/execute/mad-mix.cl
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30797>
Setting it to the same value as (or higher than) the job timeout
effectively bypasses the safety mechanism.
Let's change it to `job timeout - 5min`.
Fixes: f39ffc6911 ("ci/etnaviv: Get the gc2000_piglit manual job mostly working.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30800>
Create a new stage called etnaviv-postmerge and move the full and manual
jobs over there, to avoid entanglement with the pre-merge jobs.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
The ideal place to store the halti value is in struct etna_core_info.
Let's put it there and the determination of it into etna_gpu_new(..).
This makes it possible to reuse the halti level outside of gallium.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30394>
This bumps the req for everything, but I think that's fine, because one
part restricting to a lower rust version doesn't make much sense as we are
also not doing it generally for C or C++.
This also makes it easier for packagers to know what requires rust.
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30414>
COARSE clocks add a worst-case jitter of 10ms to the timing, as they
degrade the timing to Linux jiffy accuracy. However, they allow to skip
a syscall on platforms where the accurate version of the clock can not
be accelerated through the VDSO.
Switch to using the COARSE version of the clock when the timeout is
larger than 200ms, i.e. the accuracy of the timeout is degraded less
than 5% by the added worst-case jitter.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27079>
By using the the COARSE variant of the clock we can avoid a syscall
to fetch the current time on platforms where the more accurate
version of the clock can not be accelerated through the VDSO. The
most relevant platform with this restriction is ARM32 without the
architected timer extension, e.g. the NXP i.MX6.
The COARSE clock degrades the accuracy of the timing to Linux
jiffies, which means it adds a worst-case jitter of 10ms, which is
basically noise in relation to the 1sec holding time of the cache
and the irregular call pattern of etna_bo_cache_cleanup().
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27079>
Instead of having a hardcoded list of endian-independent format aliases
in the header, generate them from the format definitions.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29649>
Introduce unary and binary versions of the branch instruction. This will
give more ISA_OPC_BRANCH_XXX opcodes to work with. This helps to get rid
of these 'maybe' bitsets and is needed for the assembler.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30030>
In isaspec the displayname of a bitset defines what is shown in
dissassembly. The assembler only sees this representation and
needs to be able to handle it.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30030>
When there are active PMRs attached to the command buffer we can
not optimize the flush away, as that results in the queries never
reaching their expected sequence number, livelocking readers
waiting for the query result.
Fixes: 148658638e7f ("etnaviv: drm: Be able to mark end of context init")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30055>
An extended instruction uses 0x7f as opcode and stores the extended
opcode in the IMMED of src2.
Reverse engineered with the following dEQPs:
- dEQP-GLES31.functional.shaders.builtin_functions.integer.findmsb.int_lowp_vertex
- dEQP-GLES31.functional.shaders.builtin_functions.integer.findlsb.uvec3_lowp_fragment
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30010>
As we switched to an isaspec powered encoder there is no
need for this strict mapping of opc to instruction bits.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30010>
Piglit has been fixed to skip this test when no GLES 3.2 support is present.
Fixes: dfabed2fc9 ("Uprev Piglit to cf8daaf5ba90fc9b8a0e144355026e2a14c79944")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30020>
With libetnaviv_parser we are able to parse the resulting string
representation into an etna_inst and assemble that to binary.
As we are not able to parse and/or assemble we need to mark some test
cases with special flags.
This allows us to test: bin -> disasm -> parsing -> assemble
If isa_parse_str(..) is not available we skip this part of the unit
test.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
Implement the following C API's:
- isa_parse_str(..)
- isa_parse_file(..)
- isa_asm_result_destroy(..)
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
This commit adds the actual parser, which makes use of the IsaParser
derive proc macro.
It provides two public functions:
- asm_process_str(..)
Parse the provided isa representation and return an etna_asm_result.
This will be used by our unit tests.
- asm_process_file(..)
Parse a whole file full of isa and return an etna_asm_result. This
will be used by our cli assembler.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
This struct contains the result of an assembler run and will be filled
in Rust and consumed via a C API.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
This proc derive macro does the following magic:
- read static rules file
- parse isaspec xml file
- generate valid pest PEG grammar and attaches it as grammar_inline to
the ast
- calls pest_generator::derive_parser(..) to generate the parser
- creates FromPestRule trait
- creates FromPestRule impl for enums and opcodes
This is the fundation of our assembler.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
This commits adds a meta elements with the following attributes:
- has_dest: does the instruction has a dest register?
- valid_srcs: which sources need to be valid?
Is used to generate PEST grammar and defines which of the three source
registers needs to be != void.
- type: which <template> shall be used?
Must match a known template name by the last part.
E.g.: <meta type=tex"/> --> <template name="INSTR_TEX">
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
Update to etna_viv commit a2ee3de27b38.
This extends the VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM field to 4 bits,
to fix vertex shaders with 9 or more ttribute streams.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29694>
Stop hard coding accumulation buffer depth and input buffer depth to the
values for VIPNano-QI. This is allows to calculate correct tile sizes
for other cores.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28956>
Remove this logic from the gallium driver and just use the src's as
provided by nir. The special cases, where there is no 1:1 mapping, do
still exist.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28922>
