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Author SHA1 Message Date
Qiang Yu
b4f3b7c340 ac/llvm,radeonsi: lower nir_load_ring_tess_offchip_amd in abi 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23433>
 2023-06-09 10:53:08 +08:00
Qiang Yu
b44bbe7daa ac/nir,radv: add 1 dword to ES/GS item size 
This reduce LDS bank conflict and align with radeonsi,
so we don't assume LDS access 16 byte aligned for both
driver.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23314>
 2023-06-09 02:05:20 +00:00
Qiang Yu
2e1092095a ac/nir,radv: add 1 dword to LS/HS vertex stride 
This reduce LDS bank conflict and align with radeonsi,
so we don't assume LDS access 16 byte aligned for both
driver.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23314>
 2023-06-09 02:05:20 +00:00
Timur Kristóf
206cdbc440 radv: Clarify gang submit terminology. 
This is done to better match the terminology used by the kernel
and also because the follower may not always be ACE in the future.

- Gang:	a group of command streams that are submitted to
  more than one HW queue at the same time.
- Leader: the main command stream of a command buffer that works
  on the queue type of the command buffer.
- Follower: a command stream on a different HW queue that doesn't
  have a separate command buffer state and is submitted together
  with its leader.

During submission, a follower must always precede the leader in
the submitted command streams array.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23462>
 2023-06-08 15:06:52 +00:00
Rhys Perry
31c8c42f48 aco/tests: test that s_bfe bits is masked 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23464>
 2023-06-08 11:54:45 +01:00
Rhys Perry
08064a5542 aco: mask bits source of s_bfe 
The s_bfe instructions use 7 bits, not 5 like the NIR opcode requires.

No fossil-db changes (navi21).

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9162
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23464>
 2023-06-08 11:54:17 +01:00
Yonggang Luo
586391720b util: use uint32_t as the parameter of align function 
align on negative value doesn't make sense

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23421>
 2023-06-08 06:41:21 +00:00
Dave Airlie
da54b57888 radv/video: fix hevc scaling lists. 
These need some zscan conversion, that I've taken from vaapi.

v2: move to common code for it_ptr updates, add defines

Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23476>
 2023-06-08 05:34:06 +00:00
Dave Airlie
3f12103be9 radv/video: fix hevc st rps programming 
These needs to be programmed to fix some video glitches.

Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23476>
 2023-06-08 05:34:06 +00:00
Dave Airlie
f0597a1514 radv/video: rework h265 reference frame bindings. 
This reworks the ref frame bindings and allows dropping the tier_2 workaround.

Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23476>
 2023-06-08 05:34:06 +00:00
Dave Airlie
b8191cd603 radv/video: don't supply an 8-bit format for a 10-bit dpb. 
The firmware can write an 8-bit output buffer, but still needs
a 10-bit dpb allocation.

This also puts the 8-bit format after the 10-bit format though
apps should be smart enough to pick the correct one.

Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23476>
 2023-06-08 05:34:06 +00:00
Dave Airlie
b2e1e17ff6 radv/video: convert session memory requirements to outarray. 
These are just standard	outarray so use	the common code.

Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23476>
 2023-06-08 05:34:06 +00:00
Dave Airlie
28f2a6b281 radv/video: convert video format properties to an outarray 
These are just standard outarray so use the common code.

Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23476>
 2023-06-08 05:34:06 +00:00
Chia-I Wu
d0d7dda829 radv: fix non-square compressed image copy on gfx9 
There is a typo in fixup_gfx9_cs_copy.

Fixed dEQP-VK.api.copy_and_blit.*.image_to_buffer.2d_images.mip_copies_bc*_64x192_* in deqp 1.3.6.0.

Fixes: 35f053ba8c ("radv: Fix corrupted mipmap copies on GFX9+")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23483>
 2023-06-08 04:58:31 +00:00
Daniel Schürmann
e05e62c611 radv/rt: remove now dead code 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
60f9dbeb2b radv/rt: use priorities to select the next shader 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
f5428a4181 radv/debug: dump ray tracing shaders in case of a hang 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
163c97e6a7 radv/rt: separate shader compilation 
With this patch, we compile separately
 - general shaders (raygen, miss, callable)
 - closest-hit shaders
 - traversal shader (incl. all intersection / any-hit shaders)

Each shader uses the following scheme:

  if (shader_pc == shader_va) {
     <shader code>
  }
  next = select_next_shader(shader_va)
  jump next

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
defdcd2058 aco: adjust RT prolog for shader functions [disables RT] 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
302649dda1 radv/rt: adjust lower_rt_instructions() for shader functions [disables RT] 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
b33c01b00f radv/rt: set up RT shader args for separate compilation 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Friedrich Vock
365f3346f8 radv: Disable capture/replay handles 
They don't work with separate compilation. Fixing this involves some
refactoring work, which will come in future MRs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
6a5eaa25ef radv/rt: create compile_rt_prolog() function 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
09e4535f20 radv/rt: don't write cache hit feedback per stage. 
Too much boilerplate for no benefit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
7f2a569ec5 radv/rt: reference library shaders during radv_rt_fill_stage_info() 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
772b5b3758 radv/rt: add and use specialized cache search/insert functions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
62b4380acb radv/rt: pass radv_ray_tracing_pipeline to RT shader creation 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
8fb7df92c0 radv/rt: replace pCreateInfo with VkPipelineCreateFlags in rt_variables 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
d506fe3397 radv/rt: change RT main shader to MESA_SHADER_INTERSECTION 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
81e48613b9 radv/rt: implement radv_rt_nir_to_asm() 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
99466ca185 radv/rt: implement radv_nir_lower_rt_abi to lower RT shaders for separate compilation 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
d4409769c7 radv/shader_info: add RT stages to radv_get_user_data_0() 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
c75619b268 radv/rt: extend radv_pipeline_group_handle with shader VAs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
870e4d285e radv/rt: adjust shared_size when lowering hit_attribs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
393f3426b6 aco: implement select_program_rt() 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
f66f274304 aco: implement nir_intrinsic_load_resume_shader_address_amd 
Similar to p_constaddr but targeting BBs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
03c4b5b0cc nir,amd: add nir_intrinsic_store_[scalar|vector]_arg_amd to overwrite inputs 
This intrinsic must only be used at top-level CF in order
to not break SSA properties.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Daniel Schürmann
1be3a558f2 radv: add remaining RT shader args for separate compilation 
Also wrap RT args into struct {} rt for improved consistency
and remove some 'ray_' prefixes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
 2023-06-08 00:37:03 +00:00
Marek Olšák
6dc1ae1759 amd: drop support for LLVM 14 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23471>
 2023-06-07 19:56:55 +00:00
Marek Olšák
ab5662dc61 amd: drop support for LLVM 13 
We can remove the LLVM 13 Wave32 discard workaround and
SI_PROFILE_IGNORE_LLVM13_DISCARD_BUG that disabled the workaround.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23471>
 2023-06-07 19:56:55 +00:00
Marek Olšák
3a9f8730f5 amd: drop support for LLVM 12 
The demote emulation can be removed, and FS_CORRECT_DERIVS_AFTER_KILL
can be removed because it's always enabled on LLVM >= 13.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23471>
 2023-06-07 19:56:55 +00:00
Marek Olšák
4c8cc26fd8 amd: drop support for LLVM 11 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23471>
 2023-06-07 19:56:55 +00:00
Yogesh Mohan Marimuthu
7761e93c8c ac/gpu_info: rearrange if checks for dcc config 
rearrange the if checks so that there is less if checks
for newer gpus.

v2: fix block comment coding guideline (Marek Olšák)
    simplify gfx9 if condition (Marek Olšák)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23454>
 2023-06-07 19:28:29 +00:00
Yogesh Mohan Marimuthu
6f968f46fe ac/gpu_info: num_cu = 4 and gfx11 enable dcc with retile 
With num_cu = 4 in gfx11 measured power for idle, video playback and observed
power savings, hence enable dcc with retile for gfx11 with num_cu >= 4.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23454>
 2023-06-07 19:28:29 +00:00
Samuel Pitoiset
9150513242 radv: advertise VK_KHR_fragment_shader_barycentric on GFX10.3+ 
It can't be supported on older hardware because it's impossible to
determine the provoking vertex ID without LOAD_PROVOKING_VTX which is
GFX10.3+ only.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6557
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16742>
 2023-06-07 14:40:36 +00:00
Samuel Pitoiset
593fb2035d radv: gather info about nir_intrinsic_load_sample_positions_amd 
nir_intrinsic_load_barycentric_coord_at_sample is lowered before the
radv_shader_info pass and load_sample_positions_amd might be needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16742>
 2023-06-07 14:40:36 +00:00
Samuel Pitoiset
7ee8a12a62 radv: add a NIR pass that lower fragment shader barycentric intrinsics 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16742>
 2023-06-07 14:40:35 +00:00
Samuel Pitoiset
2b156c8258 radv: configure RSRC1.LOAD_PROVOKING_VTX for the fragment shader 
This enables provoking vertex info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16742>
 2023-06-07 14:40:35 +00:00
Samuel Pitoiset
b9b3560039 radv: set ROTATE_PC_PTR for custom interpolations 
This seems needed for computing stable barycentric coordinates.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16742>
 2023-06-07 14:40:35 +00:00
Samuel Pitoiset
50888ba390 radv: handle per_vertex variables when gathering FS inputs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16742>
 2023-06-07 14:40:35 +00:00