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radv/rt: implement radv_nir_lower_rt_abi to lower RT shaders for separate compilation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
This commit is contained in:
Daniel Schürmann
Marge Bot
parent
d4409769c7
commit
99466ca185
2 changed files with 119 additions and 0 deletions
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@ -26,6 +26,7 @@
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#include "bvh/bvh.h"
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#include "meta/radv_meta.h"
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#include "ac_nir.h"
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#include "radv_private.h"
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#include "radv_rt_common.h"
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#include "radv_shader.h"
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@ -88,6 +89,8 @@ struct rt_variables {
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* the correct resume index upon returning.
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*/
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nir_variable *idx;
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nir_variable *shader_va;
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nir_variable *traversal_addr;
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/* scratch offset of the argument area relative to stack_ptr */
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nir_variable *arg;
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@ -129,6 +132,10 @@ create_rt_variables(nir_shader *shader, const VkRayTracingPipelineCreateInfoKHR
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.create_info = create_info,
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};
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vars.idx = nir_variable_create(shader, nir_var_shader_temp, glsl_uint_type(), "idx");
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vars.shader_va =
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nir_variable_create(shader, nir_var_shader_temp, glsl_uint64_t_type(), "shader_va");
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vars.traversal_addr =
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nir_variable_create(shader, nir_var_shader_temp, glsl_uint64_t_type(), "traversal_addr");
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vars.arg = nir_variable_create(shader, nir_var_shader_temp, glsl_uint_type(), "arg");
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vars.stack_ptr = nir_variable_create(shader, nir_var_shader_temp, glsl_uint_type(), "stack_ptr");
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vars.shader_record_ptr =
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@ -177,6 +184,8 @@ map_rt_variables(struct hash_table *var_remap, struct rt_variables *src,
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src->create_info = dst->create_info;
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_mesa_hash_table_insert(var_remap, src->idx, dst->idx);
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_mesa_hash_table_insert(var_remap, src->shader_va, dst->shader_va);
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_mesa_hash_table_insert(var_remap, src->traversal_addr, dst->traversal_addr);
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_mesa_hash_table_insert(var_remap, src->arg, dst->arg);
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_mesa_hash_table_insert(var_remap, src->stack_ptr, dst->stack_ptr);
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_mesa_hash_table_insert(var_remap, src->shader_record_ptr, dst->shader_record_ptr);
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@ -1702,3 +1711,109 @@ create_rt_shader(struct radv_device *device, const VkRayTracingPipelineCreateInf
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return b.shader;
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}
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void
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radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
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const struct radv_shader_args *args, const struct radv_pipeline_key *key,
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uint32_t *stack_size)
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{
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nir_builder b;
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nir_function_impl *impl = nir_shader_get_entrypoint(shader);
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nir_builder_init(&b, impl);
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struct rt_variables vars = create_rt_variables(shader, pCreateInfo);
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lower_rt_instructions(shader, &vars, 0);
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if (stack_size) {
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vars.stack_size = MAX2(vars.stack_size, shader->scratch_size);
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*stack_size = MAX2(*stack_size, vars.stack_size);
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}
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shader->scratch_size = 0;
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NIR_PASS(_, shader, nir_lower_returns);
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nir_cf_list list;
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nir_cf_extract(&list, nir_before_cf_list(&impl->body), nir_after_cf_list(&impl->body));
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/* initialize variables */
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b.cursor = nir_before_cf_list(&impl->body);
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nir_ssa_def *traversal_addr = ac_nir_load_arg(&b, &args->ac, args->ac.rt.traversal_shader);
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nir_store_var(&b, vars.traversal_addr, nir_pack_64_2x32(&b, traversal_addr), 1);
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nir_ssa_def *shader_va = ac_nir_load_arg(&b, &args->ac, args->ac.rt.next_shader);
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shader_va = nir_pack_64_2x32(&b, shader_va);
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nir_store_var(&b, vars.shader_va, shader_va, 1);
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nir_store_var(&b, vars.stack_ptr,
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ac_nir_load_arg(&b, &args->ac, args->ac.rt.dynamic_callable_stack_base), 1);
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nir_ssa_def *record_ptr = ac_nir_load_arg(&b, &args->ac, args->ac.rt.shader_record);
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nir_store_var(&b, vars.shader_record_ptr, nir_pack_64_2x32(&b, record_ptr), 1);
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nir_store_var(&b, vars.arg, ac_nir_load_arg(&b, &args->ac, args->ac.rt.payload_offset), 1);
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nir_ssa_def *accel_struct = ac_nir_load_arg(&b, &args->ac, args->ac.rt.accel_struct);
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nir_store_var(&b, vars.accel_struct, nir_pack_64_2x32(&b, accel_struct), 1);
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nir_store_var(&b, vars.cull_mask_and_flags,
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ac_nir_load_arg(&b, &args->ac, args->ac.rt.cull_mask_and_flags), 1);
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nir_store_var(&b, vars.sbt_offset, ac_nir_load_arg(&b, &args->ac, args->ac.rt.sbt_offset), 1);
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nir_store_var(&b, vars.sbt_stride, ac_nir_load_arg(&b, &args->ac, args->ac.rt.sbt_stride), 1);
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nir_store_var(&b, vars.miss_index, ac_nir_load_arg(&b, &args->ac, args->ac.rt.miss_index), 1);
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nir_store_var(&b, vars.origin, ac_nir_load_arg(&b, &args->ac, args->ac.rt.ray_origin), 0x7);
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nir_store_var(&b, vars.tmin, ac_nir_load_arg(&b, &args->ac, args->ac.rt.ray_tmin), 1);
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nir_store_var(&b, vars.direction, ac_nir_load_arg(&b, &args->ac, args->ac.rt.ray_direction),
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0x7);
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nir_store_var(&b, vars.tmax, ac_nir_load_arg(&b, &args->ac, args->ac.rt.ray_tmax), 1);
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nir_store_var(&b, vars.primitive_id, ac_nir_load_arg(&b, &args->ac, args->ac.rt.primitive_id),
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1);
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nir_ssa_def *instance_addr = ac_nir_load_arg(&b, &args->ac, args->ac.rt.instance_addr);
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nir_store_var(&b, vars.instance_addr, nir_pack_64_2x32(&b, instance_addr), 1);
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nir_store_var(&b, vars.geometry_id_and_flags,
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ac_nir_load_arg(&b, &args->ac, args->ac.rt.geometry_id_and_flags), 1);
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nir_store_var(&b, vars.hit_kind, ac_nir_load_arg(&b, &args->ac, args->ac.rt.hit_kind), 1);
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/* guard the shader, so that only the correct invocations execute it */
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nir_ssa_def *shader_pc = ac_nir_load_arg(&b, &args->ac, args->ac.rt.shader_pc);
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shader_pc = nir_pack_64_2x32(&b, shader_pc);
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nir_ssa_def *cond = nir_ieq(&b, shader_pc, shader_va);
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nir_if *shader_guard = nir_push_if(&b, cond);
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shader_guard->control = nir_selection_control_divergent_always_taken;
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nir_cf_reinsert(&list, b.cursor);
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nir_pop_if(&b, shader_guard);
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/* select next shader */
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// TODO: use a priority-based selection
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b.cursor = nir_after_cf_list(&impl->body);
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shader_va = nir_load_var(&b, vars.shader_va);
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nir_ssa_def *next = nir_read_first_invocation(&b, shader_va);
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.shader_pc, next);
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/* store back all variables to registers */
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.dynamic_callable_stack_base,
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nir_load_var(&b, vars.stack_ptr));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.next_shader, nir_load_var(&b, vars.shader_va));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.shader_record,
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nir_load_var(&b, vars.shader_record_ptr));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.payload_offset, nir_load_var(&b, vars.arg));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.accel_struct, nir_load_var(&b, vars.accel_struct));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.cull_mask_and_flags,
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nir_load_var(&b, vars.cull_mask_and_flags));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.sbt_offset, nir_load_var(&b, vars.sbt_offset));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.sbt_stride, nir_load_var(&b, vars.sbt_stride));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.miss_index, nir_load_var(&b, vars.miss_index));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.ray_origin, nir_load_var(&b, vars.origin));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.ray_tmin, nir_load_var(&b, vars.tmin));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.ray_direction, nir_load_var(&b, vars.direction));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.ray_tmax, nir_load_var(&b, vars.tmax));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.primitive_id, nir_load_var(&b, vars.primitive_id));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.instance_addr, nir_load_var(&b, vars.instance_addr));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.geometry_id_and_flags,
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nir_load_var(&b, vars.geometry_id_and_flags));
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ac_nir_store_arg(&b, &args->ac, args->ac.rt.hit_kind, nir_load_var(&b, vars.hit_kind));
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/* cleanup passes */
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NIR_PASS_V(shader, nir_lower_global_vars_to_local);
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NIR_PASS_V(shader, nir_lower_vars_to_ssa);
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if (shader->info.stage == MESA_SHADER_CLOSEST_HIT ||
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shader->info.stage == MESA_SHADER_INTERSECTION)
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NIR_PASS_V(shader, lower_hit_attribs, NULL, key->cs.compute_subgroup_size);
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}
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@ -583,6 +583,10 @@ nir_shader *radv_parse_rt_stage(struct radv_device *device,
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const VkPipelineShaderStageCreateInfo *sinfo,
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const struct radv_pipeline_key *key);
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void radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
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const struct radv_shader_args *args, const struct radv_pipeline_key *key,
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uint32_t *stack_size);
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struct radv_pipeline_stage;
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nir_shader *radv_shader_spirv_to_nir(struct radv_device *device,
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