Commit graph

117072 commits

Author SHA1 Message Date
Kenneth Graunke
db878a728c iris: Make an iris_batch_get_signal_syncpt() helper.
This returns a pointer to the signalling syncpt, without incrementing
the reference count.  This can be useful for comparisons.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2019-06-26 09:49:01 -07:00
Boris Brezillon
443e530194 panfrost: Remove unneeded check in panfrost_scissor_culls_everything()
The ss local var is guaranteed to be != NULL. Get rid of this useless
check.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 09:35:25 -07:00
Alyssa Rosenzweig
d4575c3071 panfrost: Update copyright identifiers
"Collabora, Ltd." should be listed in lieu of simply "Collabora"

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Daniel Stone <daniels@collabora.com>
2019-06-26 09:10:51 -07:00
Alyssa Rosenzweig
b0e8941df1 panfrost/midgard: Reorder to permit constant bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 09:08:37 -07:00
Alyssa Rosenzweig
213b62810d panfrost/midgard: Add helper to encode constant bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 09:08:37 -07:00
Alyssa Rosenzweig
b51727ea28 panfrost/midgard: Handle negative immediate bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 09:08:37 -07:00
Rob Clark
1833827eac freedreno: correct batch_depends_on() logic
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-26 08:43:02 -07:00
Rob Clark
2b10bb6e5e freedreno: drop unused arg from fd_batch_flush()
The `force` arg has been unused for a while.. but apparently I forgot to
garbage collect it.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-26 08:43:02 -07:00
Timothy Arceri
5f809e2707 st/glsl: fix silly regression finding gs/tes variants
Fixes: d19fe5e67a ("st/glsl: support clamping color outputs in compat for gs/tes")

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-06-26 23:13:02 +10:00
Timothy Arceri
d19fe5e67a st/glsl: support clamping color outputs in compat for gs/tes
This support requires the driver to be a NIR driver as we use the
NIR lowering pass to do the clamping.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-06-26 00:36:48 +00:00
Timothy Arceri
f5f31612d3 nir: add tess support to nir_lower_clamp_color_outputs()
This will be used to add compat profile support for higher GL
versions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-06-26 00:36:48 +00:00
Sagar Ghuge
06807e1948 glsl: Fix round64 conversion function
Fix round64 function to handle round to nearest even cases specially
with positive and negative numbers with fraction part 0.5.

v2: 1) Simplify unused bits (Elie Tournier)

Fixes:
   KHR-GL45.gpu_shader_fp64.builtin.round_dvec2
   KHR-GL45.gpu_shader_fp64.builtin.round_dvec3
   KHR-GL45.gpu_shader_fp64.builtin.round_dvec4
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_double
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec2
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec3
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec4

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2019-06-25 15:19:10 -07:00
Alyssa Rosenzweig
e8f4c9f56c panfrost/ci: Add RK3288 flipflops I don't want to deal with right now
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:42:58 -07:00
Alyssa Rosenzweig
70a87a915d panfrost/ci: Update failures list
A ton of tests were fixed by this series. A few were incorrectly passing
before (QualityError, for instance) and now are explicitly failing. A
few legitimate regressions but overwhelmingly positive.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
ddf5f04edf panfrost/ci: Set MESA_GLES_VERSION_OVERRIDE=3.0
Fixes cube map tests due to disagreements between Mesa, dEQP, and the
spec...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
33f3cac1c2 panfrost/ci: Run full set of mipmap tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
f34635c699 panfrost: Advertise support for other 8-bit UNORM formats
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
310ca6ba40 panfrost: Use pipe_surface->format directly in blitter
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
5cfb4248c6 panfrost: Invert swizzle for rendering
Fixes rendering to e.g. alpha textures.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
b96f119d85 panfrost: Honour first_layer...last_layer when sampling
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
0ad17f56ae panfrost: Use the sampler_view target (not the textures)
u_blitter gets "special treatment" and uses this mechanism to cast
cube maps to 2D textures in order to texelFetch them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
faf8ad4875 panfrost/midgard: Assert guard texelFetch against cubemaps
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
124f6b541b panfrost: Zero pixels in any axis is zero pixels total
Multiplication, not addition, so switch the logic operator.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
06211f45a7 panfrost: Respect mip level when wallpapering
Fixes DATA_INVALID_FAULT raised when wallpapering while rendering to a
mipmap.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
6729912a4b panfrost/midgard: Fixup NIR texture op
In a vertex shader, a tex op should map to txl, as there *must* be a LOD
given to the hardware (implicitly or explicitly).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
17adcfc008 panfrost: Support (non-)seamless cube maps
Identify the seamless cubemap bit and passthrough the Gallium state
rather than setting unconditionally.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
3e6c6bb0af panfrost: Merge checksum buffer with main BO
This is similar to the AFBC merge; now all (non-imported) buffers use a
common backing buffer. Reenables checksumming, eliminating a performance
regression.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
a9fc1c8399 panfrost/decode: Limit MRT blend count
I thought I already fixed this. Maybe that was a dream...? Then again, I
might be dreaming now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
65e9d9b625 panfrost: Clamp tile coordinates before job submission
Fixes TILE_RANGE_FAULT raised on some tests in
dEQP-GLES3.functional.fbo.blit.*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
7005c0d83b panfrost: Use dedicated u_blitter context for wallpapers
The main ctx->blitter instance should be reserved for blits originated
from Gallium (like mipmap generation). Since wallpapering is
conceptually different -- wallpaper blits can be triggered by Gallium
blits -- the blitter pipes must be separate to avoid potential u_blitter
recursion.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
64b7bd3f90 panfrost: Sanity check layer
It doesn't make sense to try to render to multiple array elements at
once.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
eb3c09716b panfrost: Divide array_size by 6 for cubemaps
Addresses the disparity between Mali and Gallium definitions of
array_size.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
65bc56b568 panfrost: Use get_texture_address for framebuffer computations
Allows for sharing some code as well as theoretically allowing cubemap
rendering.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
3609b50a64 panfrost: Merge AFBC slab with BO backing
Rather than tracking AFBC memory "specially", just use the same codepath
as linear and tiled. Less things to mess up, I figure. This allows us to
use the standard setup_slices() call with AFBC resources, allowing
mipmapped AFBC resources.

Unfortunately, we do have to disable AFBC (and checksumming) in the
meantime to avoid functional regressions, as we don't know _a priori_ if
we'll need to access a resource from software (which is not yet hooked
up with AFBC) and we don't yet have routines to switch the layout of a
BO at runtime.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
aea3f0ac1d panfrost: Z/S can't be tiled
As far as we know, Utgard-style tiling only works for color render
targets, not depth/stencil, so ensure we don't try to tile it (rather
than compress or plain old linear) and drive ourselves into a corner.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
ad56dd4e97 panfrost: Enable mipmapping
Now the autogeneration of mipmaps is working (via u_blitter), we can
finally enable mipmaps!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
5aeffa9517 panfrost: Enable blitting
Now that all the prerequisites breaking u_blitter are fixed, we can
finally hook up panfrost_blit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
06d192c742 panfrost: Allow texelFetch for wallpaper blits
We just implemented the routine; we may as well use it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
f4bb7f096c panfrost/midgard: Implement texelFetch (2D only)
txf instructions can result from blits, so handle them rather than
crash. Only works for 2D textures (not even 2D array texture) due to a
register allocation constraint that may not be sorted for a while.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
4ac42f2b38 panfrost: Skip flushes only for wallpapers, not any blit
We need the flush from u_blitter for a normal blit (e.g. for mipmaps);
it's only wallpaper-related blits that are special-cased.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
ffcc4d1c4e panfrost: Handle generate_mipmap ourselves
To avoid interference with the wallpaper code, we need to do some state
tracking when generating mipmaps. In particular, we need to mark the
generated layers as invalid before generating the mipmap, so we don't
try to backblit them if they already had content.

Likewise, we need to flush both before and after generating a mipmap
since our usual set_framebuffer_state flushing isn't quite there yet.
Ideally better optimizations would save the flush but I digress.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Alyssa Rosenzweig
f57dfe4cdd panfrost: Disable mipmapping if necessary
If a mipfilter is not set, it's legal to have an incomplete mipmap; we
should handle this accordingly. An "easy way out" is to rig the LOD
clamps.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:17 -07:00
Kenneth Graunke
748e5dac72 intel/blorp: Disable sampler state prefetching on Gen11
Sampler state prefetching is broken on Gen11, and WA_160668216 says
to disable it.  Apparently sampler state prefetching also has basically
zero impact on performance, so we don't need to worry there.

i965, anv, and iris already handle this correctly, but we missed BLORP.
Ideally the kernel should globally disable this by writing SARCHKMD, at
which point we wouldn't have to worry about it.  But let's be defensive
and handle it ourselves too.

v2: separate out from BTP workaround in case we change that eventually

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> [v1]
2019-06-25 13:29:31 -07:00
Jason Ekstrand
0a364a4a74 anv/descriptor_set: Only write texture swizzles if we have an image view
When immutable samplers are set we call write_image_view with a NULL
image view.  This causes issues on IVB where we have to fake texture
swizzling.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110999
Fixes: d2aa65eb18 "anv: Emulate texture swizzle in the shader when..."
2019-06-25 19:43:25 +00:00
Chia-I Wu
74786b3aa3 virgl: add VIRGL_DEBUG_XFER
When set, do as requested and skip any transfer optimization.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-25 12:01:45 -07:00
Chia-I Wu
e93d918b65 virgl: add VIRGL_DEBUG_SYNC
When set, wait after every each flush.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-25 12:01:43 -07:00
Chia-I Wu
119b5701e1 virgl: fix the value of VIRGL_DEBUG_BGRA_DEST_SWIZZLE
VIRGL_DEBUG_BGRA_DEST_SWIZZLE should use bit 3.  Make some cosmetic
changes as well.

Fixes: a478e56fbd
    virgl: Add debug flag to bypass driconf to enable the BGRA tweaks

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-25 12:01:14 -07:00
Samuel Pitoiset
8ea7ee1536 radv: rename and re-document cache flush flags
SMEM and VMEM caches are L0 on gfx10. Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-25 18:38:37 +02:00
Samuel Pitoiset
5411f47056 radv: set DISABLE_CONSTANT_ENCODE_REG to 1 for Raven2
Ported from RadeonSI, will be emitted for GFX10 too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-25 16:45:15 +02:00
Samuel Pitoiset
34bef8a0d7 radv: clear CMASK layers instead of the whole buffer on GFX8
This reduces the size of fill operations needed to clear CMASK
for layered color textures.

GFX9 unsupported for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-25 16:36:28 +02:00