Commit graph

3367 commits

Author SHA1 Message Date
Qiang Yu
50c0451424 nir/linker: rename replace_constant_input to replace_varying_input_by_constant_load
To align with replace_varying_input_by_uniform_load and better
describe what it does.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12613>
2021-10-13 04:45:15 +00:00
Qiang Yu
2604625043 nir/linker: support uniform when optimizing varying
Varying assigned from uniform won't change after interpolation,
so move uniform load to fragment shader to eliminate the varying.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12613>
2021-10-13 04:45:15 +00:00
Filip Gawin
28a6e45a0f nir: avoiding reading unitialized memory when using nir_dest_copy
Deeper in chain of calls, function "src_has_indirect" is used (which
reads "is_ssa" and "reg.indirect").

Fixes: d1eae6f36b ("nir: Properly clean up nir_src/dest indirects")

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13317>
2021-10-13 02:21:20 +00:00
Connor Abbott
b516208a55 nir/lower_ubo_vec4: Fix align_mul=8 special case
In order for the load to never straddle the load can't extend past 8
bytes, not 16. For example a vec2 load with align_mul = 8 and
align_offset = 4 can straddle.

Fixes assertion failures when we stop pushing UBOs in the preamble on
a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Jason Ekstrand
878d8d96c7 nir/lower_discard_or_demote: Fix metadata
Passes generally shouldn't use nir_metadata_all unless they don't change
the program in any significant way.  Some of these passes insert new
instructions so they should definitely not be preserving most of it.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13261>
2021-10-08 23:24:49 +00:00
Chia-I Wu
8cce6281e6 util/vector: make util_vector_init harder to misuse
Make u_vector_init a wrapper to u_vector_init_pot.  Let both take
(element_count, element_size) as parameters.

Motivated by eed0fc4caf ("vulkan/wsi/wayland: fix an invalid
u_vector_init call")

v2: rename u_vector_init_pot to u_vector_init_pow2

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13201>
2021-10-08 00:15:11 +00:00
Boris Brezillon
56251f924d nir: Add a nir_sysvals_to_varyings() helper
Allow backends to turn some sysvals into input varyings so the frontend
(in our case spirv_to_nir()) doesn't have to bother selecting which
one is expected.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13017>
2021-10-07 19:45:35 +00:00
Jason Ekstrand
b71bdc3404 nir/algebraic: Add some opts for comparisons of comparisons
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13167>
2021-10-07 18:21:11 +00:00
Jason Ekstrand
7abf3955ca nir/algebraic: Add some boolean optimizations
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13167>
2021-10-07 18:21:11 +00:00
Jason Ekstrand
c8b2be0b95 nir/algebraic: Lower fisfinite
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13167>
2021-10-07 18:21:11 +00:00
Rhys Perry
f3723822a4 nir/lower_tex: add lower_to_fragment_fetch_amd
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12214>
2021-10-07 15:36:39 +00:00
Rhys Perry
225fe37c14 nir: add _amd suffix to fragment_mask_fetch and fragment_fetch texops
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12214>
2021-10-07 15:36:39 +00:00
Marcin Ślusarz
3a18963b08 nir/print: pad 64-bit constants with zeroes
... just like other-size constants are.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13223>
2021-10-07 10:49:15 +00:00
Emma Anholt
7dde279db5 nir-to-tgsi: Avoid emitting TXL just for lod 0 on non-vertex shaders.
Prompted by comparing virgl fails and finding that it has issues with
immediate args to TXL/TXB, at least.

Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12800>
2021-10-06 03:44:17 +00:00
Ian Romanick
cb28361642 nir/algebraic: Small optimizations for SpvOpFOrdNotEqual and SpvOpFUnordEqual
No shader-db changes on any Intel platform.

Fossil-db results:

All Intel platforms had similar results. (Ice Lake shown)
Instructions in all programs: 144380118 -> 143692823 (-0.5%)
SENDs in all programs: 6920822 -> 6920822 (+0.0%)
Loops in all programs: 38299 -> 38299 (+0.0%)
Cycles in all programs: 8434782176 -> 8423078994 (-0.1%)
Spills in all programs: 206830 -> 204469 (-1.1%)
Fills in all programs: 318737 -> 313660 (-1.6%)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12320>
2021-10-06 01:53:47 +00:00
Alyssa Rosenzweig
3e8f540753 nir: Add Mali-specific derivative opcodes
Add derivative opcodes fddx_must_abs_mali/fddy_must_abs_mali satisfying:

   fabs(fdd*_must_abs_mali(v)) = fabs(fdd*(v))

The sign of their result is undefined.

On Bifrost and Valhall, these unsigned derivatives can be implemented
more efficiently than the correctly-signed counterparts, since the sign
fixup requires extra ALU instructions. On backends where this is the
case, it is useful to optimize fabs(fdd*(v)) to
fabs(fdd*_must_abs_mali(v)). This pattern comes up with the GLSL builtin
`fwidth`.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12332>
2021-10-06 00:40:57 +00:00
Lionel Landwerlin
d0a3a11258 nir/lower_io: preserve all metadata when no progress
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13168>
2021-10-05 11:23:23 +00:00
Marcin Ślusarz
e26328582a nir: preserve all metadata when nir_opt_vectorize doesn't make progress
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13189>
2021-10-05 10:02:54 +00:00
Marcin Ślusarz
54df09c8d4 nir: preserve all metadata when nir_propagate_invariant doesn't make progress
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13189>
2021-10-05 10:02:54 +00:00
Marcin Ślusarz
804c56f1a2 nir: preserve all metadata when nir_lower_int_to_float doesn't make progress
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13189>
2021-10-05 10:02:54 +00:00
Boris Brezillon
7cd402c9c8 nir/lower_blend: Shrink blended result if needed
Make sure the new and old sources have the same number of components,
otherwise the NIR validation pass complains.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Boris Brezillon
3e07b8d4f8 nir/lower_blend: Make sure we're not passed scaled formats
SCALED formats are interpreted as floats, but not in the usual [0, 1]
or [-1, 1] range, meaning that the blend lowering logic can't directly
apply to those. Assert that the format being passed is not a scaled
format.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Boris Brezillon
15b4cab4d5 nir/lower_blend: Don't lower RTs whose format is set to NONE
The caller doesn't necessarily want to lower blend operations on all
render targets since some of them might be supported natively (panvk
will be in that case). Let's just skip RTs that have a format set to
PIPE_FORMAT_NONE to allow that.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Boris Brezillon
637cd5ac00 nir/lower_blend: Pad src to a 4-component vector
nir_ssa_for_src() is not supposed to pad the src vector if
dst->num_components > src->num_components. Let's pad things explicitly
with nir_pad_vector().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Boris Brezillon
641bed3103 nir: Make sure src->num_components < dst->num_components in nir_ssa_for_src()
The NIR validation complains if the swizzle accesses a component that's
not present in the source.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
2021-09-30 16:54:42 +02:00
Lionel Landwerlin
daa8a81d99 nir: fix opt_memcpy src/dst mixup
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: f6667cb0ce ("nir: Add a memcpy optimization pass")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13079>
2021-09-28 16:36:08 +00:00
Rhys Perry
e43007af56 nir/opt_if: add opt_if_rewrite_uniform_uses
Turns:
if (a == (b=readfirstlane(a)))
   use(a)
into:
if (a == (b=readfirstlane(a)))
   use(b)

Improves divergence analysis and lets us scalarize use(a). Improves
Cyberpunk 2077 performance.

fossil-db (Sienna Cichlid, Cyberpunk 2077):
Totals from 57 (10.56% of 540) affected shaders:
VGPRs: 4904 -> 4040 (-17.62%)
CodeSize: 624360 -> 626828 (+0.40%); split: -0.06%, +0.46%
MaxWaves: 656 -> 824 (+25.61%)
Instrs: 119770 -> 119447 (-0.27%); split: -0.49%, +0.22%
Latency: 1950256 -> 1633110 (-16.26%); split: -16.26%, +0.00%
InvThroughput: 364852 -> 292089 (-19.94%)
VClause: 1512 -> 1008 (-33.33%)
SClause: 2693 -> 3196 (+18.68%)
Copies: 10050 -> 9955 (-0.95%); split: -3.34%, +2.40%
Branches: 3476 -> 3547 (+2.04%)
PreSGPRs: 4003 -> 5076 (+26.80%)
PreVGPRs: 4709 -> 3810 (-19.09%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12472>
2021-09-24 18:41:18 +00:00
Rhys Perry
69f9a96af1 nir: add nir_src_components_read()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12472>
2021-09-24 18:41:18 +00:00
Caio Marcelo de Oliveira Filho
240e60ba76 nir/lower_io_to_vector: Allow Task/Mesh to load from outputs
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12951>
2021-09-24 14:35:15 +00:00
Bas Nieuwenhuizen
0d8bd8518d nir: Support ray launch size in divergence analysis.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
56b06c09b4 nir: Add AMD rt intrinsics.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
b6be96a2bd radv: Modify load_sbt_amd intrinsic to get the descriptor.
That way we can get the address to the entry, which is needed for
some nir builtins because extra data in the entry can be used as
shader input.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Timur Kristóf
872d21820f nir: Exclude non-generic patch variables from get_variable_io_mask.
These are I/O variables which are not going to be removed anyway.
However, get_variable_io_mask handles their location incorrectly.

Found using the GCC undefined behavior sanitizer.
Fixes the following error:

runtime error:
shift exponent 4294967258 is too large
for 64-bit type 'long unsigned int'

Closes: #5319
Fixes: cf5f8f55c3
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12719>
2021-09-20 18:08:16 +00:00
Ian Romanick
d7ba52cce9 nir/edgeflags: Add a flag to indicate the edge flag input is needed
Most modern hardware needs the edge flag added as a hidden vertex input
and needs code added to the vertex shader to copy the input to an
output.  Intel hardware is a little different.  Gfx4 and Gfx5 hardware
works in the previously described mannter.  Gfx6+ hardware needs the
edge flag as a specific vertex shader input, and that input is magically
processed by fixed-function hardware without need for extra shader code.

This flag signals only that the vertex shader input is needed.  It would
be nice if we could decouple adding the vertex shader input from
generating the copy-to-output code, but that has proven to be
challenging.  Not having that code causes other passes to want to
eliminate that shader input.

v2: Convert conditional to assertion.  This pass is only called for
vertex shaders.  Suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12858>
2021-09-17 16:36:08 -07:00
Rhys Perry
a1af902531 nir/algebraic: distribute fmul(fadd(a, b), c) when b and c are constants
This allows for more MAD/FMA instructions to be created.

fossil-db (Sienna Cichlid):
Totals from 50134 (33.46% of 149839) affected shaders:
VGPRs: 2436536 -> 2436000 (-0.02%); split: -0.05%, +0.03%
SpillSGPRs: 13136 -> 13135 (-0.01%); split: -0.02%, +0.02%
CodeSize: 206621424 -> 206278292 (-0.17%); split: -0.23%, +0.07%
MaxWaves: 1116804 -> 1117448 (+0.06%); split: +0.07%, -0.01%
Instrs: 38977460 -> 38862886 (-0.29%); split: -0.33%, +0.04%
Latency: 832425389 -> 827432260 (-0.60%); split: -0.63%, +0.03%
InvThroughput: 184193457 -> 183563350 (-0.34%); split: -0.37%, +0.03%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7458>
2021-09-17 17:28:26 +00:00
Jason Ekstrand
6c7d23e6ca nir: Stop sweeping indirects
They're no longer ralloc'd.

Fixes: 879a569884 "nir: Switch from ralloc to malloc for NIR instructions."
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12884>
2021-09-16 11:28:36 +00:00
Jason Ekstrand
d1eae6f36b nir: Properly clean up nir_src/dest indirects
Now that they're no longer ralloc'd, we have to be much more careful
about indirects.  We have to make sure every time a source or
destination is overwritten, its indirect (if any) is freed.  We also
have to choose a memory ownership convention for the rewrite functions.
Assuming that they will be called with the source from some other
instruction, we choose to always make a copy of the indirect (if any).
It's the responsibility of the caller to ensure its copy of the indirect
is freed.

Unfortunately, all this extra logic is going to make
nir_instr_rewrite/move_src/dest more expensive because they now have
all the logic of nir_src/dest_copy instead of a simple struct
assignment.  Fortunately, the vast majority of rewrite calls are done by
nir_ssa_def_rewrite_uses which is an SSA-only fast-path.

Fixes: 879a569884 "nir: Switch from ralloc to malloc for NIR instructions."
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12884>
2021-09-16 11:28:36 +00:00
Emma Anholt
aed4c0b5a9 nir: Drop the unused instr arg for src/dest copy functions.
Now that we don't use ralloc, we don't need this arg to get at the right
ralloc ctx.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
2021-09-14 17:53:06 +00:00
Emma Anholt
879a569884 nir: Switch from ralloc to malloc for NIR instructions.
By replacing the 48-byte ralloc header with our exec_node gc_node (16
bytes), runtime of shader-db on my system across this series drops
-4.21738% +/- 1.47757% (n=5).

Inspired by discussion on #5034.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
2021-09-14 17:53:06 +00:00
Emma Anholt
feee5e6974 nir/tests: Fix transmuting an SSA dest to be non-SSA
With the de-ralloc changes, having the register dest not have its .reg
properly initialized caused crashes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
2021-09-14 17:53:06 +00:00
Emma Anholt
1edff520e2 nir/lower_phis_to_scalar: Use nir_instr_free() to free instrs.
Preparation for de-rallocing instrs.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
2021-09-14 17:53:06 +00:00
Emma Anholt
d1a2870f78 nir: Add all allocated instructions to a GC list.
Right now we're using ralloc to GC our NIR instructions, but ralloc has
significant overhead for its recursive nature so it would be nice to use a
simpler mechanism for GCing instructions.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
2021-09-14 17:53:06 +00:00
Emma Anholt
22788d68eb nir: Consistently pass the instr to nir_src_copy().
The arg says it's supposed to be the instr, not the shader.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
2021-09-14 17:53:05 +00:00
Emma Anholt
5e37cfb7fe nir: Consistently pass the shader to the shader arg of instr creation.
We were using the ralloc parent in some places, which should work out to
be the shader I think, but to de-ralloc the instrs we should just pass the
existing shader pointer in.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
2021-09-14 17:53:05 +00:00
Emma Anholt
7a4bbe60c1 nir/from_ssa: Use nir_instr_free() to free instrs instead of ralloc.
This code was being tricky with passing a mem_ctx instead of the shader,
then freeing the mem_ctx when the pass was done and all the parallel
copies had been removed from the shader.  Use the right type for instr
creation and do a bit of manual list management to prepare the way for
non-ralloc NIR instrs.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
2021-09-14 17:53:05 +00:00
Emma Anholt
b99efb8af0 nir: Pull the instr list free function out to a helper.
With the de-rallocing, we're going to have some more places that free a
list of instrs.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
2021-09-14 17:53:05 +00:00
Emma Anholt
36d9bdca0b nir: Add a nir_instr_free() to replace ralloc_free(instr).
This will gain another step shortly.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
2021-09-14 17:53:05 +00:00
Ian Romanick
7956a701d8 nir/lower_gs_intrinsics: Make nir_lower_gs_intrinsics be idempotent
Calling this lower pass twice in a row would cause spurious
set_vertex_and_primitive_count(0, undef) intrinsics after the proper
set_vertex_and_primitive_count intrinsic.  This pretty much turns any
geometry shader into garbage.

Fix this by treating nir_intrinsic_emit_vertex_with_counter and
nir_intrinsic_end_primitive_with_counter just like the non-_with_counter
versions.  If no blocks would need set_vertex_and_primitive_count
intrinsics added, exit the pass before doing any work.  This prevents
the need for DCE to do extra clean up later.

Since this pass is potentially called multiple times via multiple
invocations of a finalize_nir callback, it is (hypothetically?) possible
that control flow could be changed to add new blocks that need this
intrinsic.  The check implemented in this commit should be robust
against that possibility.

v2: Add a_block_needs_set_vertex_and_primitive_count.  Suggested by
Timur.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12802>
2021-09-14 09:13:07 -07:00
Ian Romanick
edf357b233 nir/lower_gs_intrinsics: Return progress if append_set_vertex_and_primitive_count makes progress
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 542d40d698 ("nir: Add new GS intrinsics that maintain a count of emitted vertices.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12802>
2021-09-14 09:12:47 -07:00
Bas Nieuwenhuizen
b05cd10b8e nir: Avoid visiting instructions multiple times in nir_instr_free_and_dce.
Sadly need to poke a bit in the src internals to avoid using yet another
heap allocated datastructure.

Fixes: 5251548572 ("nir: Add a nir_instr_remove that recursively removes dead code.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5323
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12726>
2021-09-09 21:35:03 +00:00