In the past we were doing per-quad lod for cube maps (when no_quad_lod
wasn't set), however commit d413fd0219 ("gallivm: Always take the
per-pixel LOD path for cubemaps.") unconditionally enabled calculating
per-pixel derivatives.
However, the actual lod calculation was still only done per quad, which
probably doesn't make much sense, so unconditionally enable taking the
per-pixel lod path for cubemaps (for op_is_lodq we always force
no_quad_lod to false in any case so there's no difference there neither).
v2: adjust ci results accordingly
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18126>
This is mostly just cosmetic, since the index bias will be ignored.
(The multi draw function already initializes this to 0 too.)
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18126>
Each logical device can point to its physical device intel_device_info
saving at least one intel_device_info.
This also allow us to set 'const' to avoid values in intel_device_info
being changed by mistake.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17897>
If we don't recognize the model, dev->model will be NULL. In that case, we can't
dereference dev->model to get the tilebuffer size. If we do, we'll segfault,
instead of gracefully refusing to probe and loading the swrast instead.
Fixes: 96d65b47c7 ("panfrost: Use implementation-specific tile size")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18115>
Additionally add support for PIPE_CAP_CLEAR_SCISSORED since we are already
touching the scissor state.
Fixes various gnome-shell rendering artifacts.
v2: Remove NEW_SCISSOR as clear now updates scissor registers explicitly
v3: Reset scissor_off state since its not off now after clear
Cc: mesa-stable
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18137>
textureCompressionBC is just a short-hand to know is *all* BPTC formats
are supported. We're already checking per format, so we don't need this
coarser check.
Besides, it's also kinda wrong; textureCompressionBC also requires all
BC formats, not just BPTC. In other words, all DXT formats and RGTC
formats were missing from the check.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17986>
Alpha-to-coverage acts like discard and happens after FS ends,
so like with discard LRZ write should be disabled.
With discard we don't know at the moment of binning whether
fragment would be not discarded, so we cannot write its depth to LRZ.
Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18102>
Thos are only included once, so just move the code into the
corresponding .comp files.
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17963>
SPIR-V shift ops unlike NIR have undefined behavior if shift count
larger than or equalt to bitwidth.
This means that true translation of NIR ishl/ishr/ushr to SPIR-V requires
masking like that done in gallivm.
This was seen in the case of soft fp64 in cts case
KHR-GL46.gpu_shader_fp64.builtin.ceil_double.
Cc: mesa-stable
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18074>
Loading indirectly from a register that was just written to
doesn't work on R600 class hardware, so add a NOP group with
the address register load being emitted in the t-slot. to make
sure that the register write was finished.
Fixes: 33765aa92a
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
On R600 and R700 class hardware the input declaration order maps
directly to the register the hardware writes the inputs to, so
make all interpolated inputs come first, and only then emit the
system values like POS or FACE.
Related: #7035
Fixes: 33765aa92a
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
textureGatherOffsets always takes a highp array of constants. As
per the discussion in [1] trying to lower the precision results in segfault
later on in the compiler as textureGatherOffsets will end up being passed
a temp when its expecting a constant as required by the spec.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16547#note_1393704
Fixes: b83f4b9fa2 ("glsl: Add an IR lowering pass to convert mediump operations to 16-bit")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18101>
Allows following tests to pass.
dEQP-VK.wsi.android.swapchain.create#image_swapchain_create_info
dEQP-VK.wsi.android.swapchain.simulate_oom#image_swapchain_create_info
Venus code was used as example.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>
Android CDD has additional requirements that must be met in order to
enable 1.1+:
- samplerYcbcrConversion
- VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
- VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
- VK_ANDROID_external_memory_android_hardware_buffer >= v2
Requirements are checked by:
android.graphics.cts.VulkanFeaturesTest#testVulkan1_1Requirements CTS
Fixes: 2686c5419d ("v3dv: add Android support")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>
vk_common_AcquireImageANDROID and vk_common_QueueSignalReleaseImageANDROID
expect sync_fd import/export to be enabled, otherwise they crashes
while trying to ImportSemaphoreFdKHR() / GetSemaphoreFdKHR().
Features was disabled on Linux to skip sync_fd CTS tests, which is using
late vkEvent signalling which causes deadlock / dEQP timeout on v3dv.
One of the options was implementing blocking v3dv-specific
AcquireImageANDROID / QueueSignalReleaseImageANDROID to avoid importing
/ exporting sync_fd, but since these features are also required by CDD
for Vulkan 1.1 and above, it was decided to enable the extensions for
Android in exchange of a few failed dEQP tests (which should not cause
any issues in non-dEQP scenarious).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6977
Fixes: 316728a55b ("v3dv: Switch to the common submit framework")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>
Right now even the simplest mesh test (func.mesh.basic.mesh from crucible) fails like this:
ASSERT: Scalar MESH validation failed!
load_payload(16) vgrf11+0.0:F, vgrf8:D
../../src/intel/compiler/brw_fs_validate.cpp:61: inst->dst.offset / REG_SIZE + regs_written(inst) <= alloc.sizes[inst->dst.nr]
Because we try to load 8 regs with LOAD_PAYLOAD in SIMD16 mode.
Fixes: 349a040f68 ("intel/fs: Make logical URB write instructions more like other logical instructions")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18075>
This reverts commit 23e5b910c5.
Reason for revert:
It's causing the regression for H264 transcoding. We will Enable EFC
once we verify all corner cases and as of now disabling
Signed-off-by: Ikshwaku Chauhan <ikshwaku.chauhan@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17869>
This backend lowering code has been dead since the removal of i965 -
nothing in the current source tree ever sets the flag.
This is handled by iris_setup_uniforms() and crocus_setup_uniforms().
Variable group size does not appear to be a feature in anv.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18055>
KVM requires memory mapping to be aligned to page size, otherwise it
refuses to do the mapping. In particular this causes KVM mapping errors
when llvmpipe is used by virtio-gpu on host and guest tries to map buffer
that has a persistent mapping, i.e. it tries to map the llvmpipe's host
blob/buffer. Mesa virgl driver uses host blobs only for the buffers with
persistent mapping, hence let's align buffer allocations to the page size
when the persistence flag is set to fix the KVM fault.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18053>
the non-negotiated path assumes that drivers know what implicit modifiers they're
using, but zink doesn't know what it's doing, so instead try to copy the
swapchain's modifier and reuse that since in theory it should work
Fixes: 247b8f2924 ("zink: add all format modifiers when adding for dmabuf export")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18095>
the spec mandates that all modifiers passed to the driver be valid, so
iterate through all of them and delete the invalid ones
Fixes: 247b8f2924 ("zink: add all format modifiers when adding for dmabuf export")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18095>
if srgb-ness isn't supported by the driver for dmabuf, bail out early with an
error message with the assumption that this would later (maybe) explode when
trying to create a view for srgb framebuffer
ref !17900
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18095>
get_ssa_temp's and NIR's bit size can differ for scalar sources.
This causes broken packing of the MIMG operands with A16/G16.
Fixes: f5f73db846 ("aco: Support 16bit sources for texture ops.")
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18008>
Separately track descriptor set layouts for pools with
FREE_DESCRIPTOR_SET disabled, instead of reusing
`radv_descriptor_pool::entries`. This saves 8 bytes for each entry and
also avoids some indirection.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16541>
The lp_rasterizer is shared across contexts, and lp_rast_fence called
without holding rast_mutex could race with rast_mutex being replaced and
unref'd on a different thread.
Fixes: a680fd078c ("llvmpipe: make last_fence a screen/rast object not a context one.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18116>
this is cumbersome to detect, so detect it here
the flag denotes the use of either bindless texture operations
or shader variables such that drivers can infer the use of bindless
descriptor management functionality
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18088>
Simplify things for the next patch.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Mostly because simple_mtx_assert_locked() will come in handy during
locking re-work.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
*Technically* we should be unlocking with the 'disp' and not the 'dpy'
(even though they are the same thing).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
